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32-channel, 3 v/5 v, single-supply, 12-bit, voltage output dac ad5383 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures guar ant e e d m o not o ni c i n l e r ro r: 1 l s b m a x o n - c hip 1.25 v/ 2.5 v , 10 p p m/ c ref e renc e t e mper a t ure r a nge: C40c t o + 85c r a il-t o - r a i l out p ut amplifier p o w e r- down mode p a ck age t y pe: 100-le ad l q fp (14 mm 14 m m ) u s er int e r f ac es : pa r a l l e l s e rial (spi?/qspi?/micr owire?/dsp c o mpa t ible , f e a t uring da ta r eadback) i 2 c? c o mpa t ibl e integr a t e d fu nc ti o n s channel monitor simultaneo us o u tput update via ld a c clear f u nc tion t o user pr ogr a mmable c o de a m plifier boost mode t o optimiz e sle w r a t e u s er pr ogr a mmable off s et a n d gain adjust t o ggle mode enables squar e wa v e gener a ti on t h ermal monitor applic a t io ns v a riable optic a l a t t e nuat ors ( v o a ) le v e l setting ( a te) o p ti c a l micr o - elec tr o - mecha n ic al sy st ems ( m ems) c o n t r o l sy st em s instrumen t a t ion func ti on a l bl ock di a g r a m r r vout0 dac 0 dac reg 0 input reg 0 12 12 12 12 12 12 m reg 0 c reg 0 1.25v/2.5v reference power-on reset r r vout1 vout2 vout3 vout4 vout5 dac 1 dac reg 1 input reg 1 12 12 12 12 12 12 m reg 1 c reg 1 r r vout6 dac 6 dac reg 6 input reg 6 12 12 12 12 12 12 m reg 6 c reg 6 r r vout7 vout8 dac 7 dac reg 7 input reg 7 12 12 12 12 12 12 m reg 7 c reg 7 4 03734-0-001 fifo + state machine + control logic interface control logic db11/(din/sda) db10/(sclk/scl) db9/(spi/i2c) db8 a4 a0 reg 0 reg 1 reset busy clr mon_in1 mon_in2 mon_in3 mon_in4 pd ser/par fifo en cs/(sync/ad0) wr/(dcen/ad1) sdo 36-to-1 mux v out 0 ???v out 31 mon_out ldac vout31 dvdd ( 3) dgnd ( 3) avdd ( 4) agnd (4) dac gnd ( 4) refgnd refout/refin signal gnd ( 4) ad5383 db0 fi g u r e 1 .
ad5383 rev. 0 | page 2 of 40 table of contents general description ......................................................................... 3 specifications ..................................................................................... 4 ad5383-5 specifications ............................................................. 4 ad5383-3 specifications ............................................................. 6 ac characteristics ........................................................................ 7 timing characteristics ..................................................................... 8 serial interface timing ................................................................ 8 i c serial interface timing 2 ........................................................ 10 parallel interface timing ........................................................... 11 absolute maximum ratings .......................................................... 13 pin configuration and function descriptions ........................... 14 te r m i no l o g y .................................................................................... 17 typical performance characteristics ........................................... 18 functional description .................................................................. 21 dac architecturegeneral ..................................................... 21 data decoding ............................................................................ 21 on-chip special function registers (sfr) ............................ 22 sfr commands .......................................................................... 22 hardware functions ....................................................................... 25 reset function ............................................................................ 25 asynchronous clear function .................................................. 25 busy and ldac functions ...................................................... 25 fifo operation in parallel mode ............................................ 25 power-on reset .......................................................................... 25 power-down ............................................................................... 25 ad5383 interfaces .......................................................................... 26 dsp, spi, microwire compatible serial interfaces .......... 26 i c serial interface 2 ..................................................................... 28 parallel interface ......................................................................... 30 microprocessor interfacing ....................................................... 31 application information ................................................................ 33 power supply decoupling ......................................................... 33 typical configuration circuit .................................................. 33 ad5383 monitor function ....................................................... 34 toggle mode function ............................................................... 34 thermal monitor function ....................................................... 34 optical attenuators .................................................................... 35 utilizing the ad5383 fifo ....................................................... 36 outline dimensions ....................................................................... 37 ordering guide .......................................................................... 37 revision history 5/04revision 0: initial version
ad5383 rev. 0 | page 3 of 40 general description the ad5383 is a complete, single-supply, 32-channel, 12-bit dac available in a 100-lead lqfp package. all 32 channels have an on-chip output amplifier with rail-to-rail operation. the ad5383 includes a programmable internal 1.25 v/2.5 v, 10 ppm/c reference, an on-chip channel monitor function that multiplexes the analog outputs to a common mon_out pin for external monitoring, and an output amplifier boost mode that allows optimization of the amplifier slew rate. the ad5383 contains a double-buffered parallel interface that features a 20 ns wr pulse width, an spi/qspi/microwire/dsp compatible serial interface with interface speeds in excess of 30 mhz, and an i 2 c compatible interface that supports a 400 khz data transfer rate. an input register followed by a dac register provides double buffering, allowing the dac outputs to be updated indepen- dently or simultaneously using the ldac input. each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any dac channel. power consumption is typically 0.25 ma/channel with boost off. table 1. other high channel count, low voltag e, single supply dac products in portfolio model resolution av dd range output channels linearity error (lsb) package description package option ad5380bst-5 14 bits 4.5 v to 5.5 v 40 4 100-lead lqfp st-100 ad5380bst-3 14 bits 2.7 v to 3.6 v 40 4 100-lead lqfp st-100 ad5384bbc-5 14 bits 4.5 v to 5.5 v 40 4 100-lead cspbga bc-100 ad5384bbc-3 14 bits 2.7 v to 3.6 v 40 4 100-lead cspbga bc-100 ad5381bst-5 12 bits 4.5 v to 5.5 v 40 1 100-lead lqfp st-100 ad5381bst-3 12 bits 2.7 v to 3.6 v 40 1 100-lead lqfp st-100 ad5382bst-5 14 bits 4.5 v to 5.5 v 32 4 100-lead lqfp st-100 ad5382bst-3 14 bits 2.7 v to 3.6 v 32 4 100-lead lqfp st-100 ad5390bst-5 14 bits 4.5 v to 5.5 v 16 3 52-lead lqfp st-52 ad5390bcp-5 14 bits 4.5 v to 5.5 v 16 3 64-lead lfcsp cp-64 ad5390bst-3 14 bits 2.7 v to 3.6 v 16 3 52-lead lqfp st-52 ad5390bcp-3 14 bits 2.7 v to 3.6 v 16 3 64-lead lfcsp cp-64 ad5391bst-5 12 bits 4.5 v to 5.5 v 16 1 52-lead lqfp st-52 ad5391bcp-5 12 bits 4.5 v to 5.5 v 16 1 64-lead lfcsp cp-64 ad5391bst-3 12 bits 2.7 v to 3.6 v 16 1 52-lead lqfp st-52 ad5391bcp-3 12 bits 2.7 v to 3.6 v 16 1 64-lead lfcsp cp-64 ad5392bst-5 14 bits 4.5 v to 5.5 v 8 3 52-lead lqfp st-52 ad5392bcp-5 14 bits 4.5 v to 5.5 v 8 3 64-lead lfcsp cp-64 ad5392bst-3 14 bits 2.7 v to 3.6 v 8 3 52-lead lqfp st-52 ad5392bcp-3 14 bits 2.7 v to 3.6 v 8 3 64-lead lfcsp cp-64 table 2. 40-channel, bipo lar voltage output dac model resolution analog supplies output channe ls linearity error (lsb) package package option ad5379abc 14 bits 11.4 v to 16.5 v 40 3 108-lead cspbga bc-108
ad5383 rev. 0 | page 4 of 40 specifications ad5383-5 specifications table 3. av dd = 4.5 v to 5.5 v; dv dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; external refin = 2.5 v; all specifications t min to t max , unless otherwise noted parameter ad5383-5 1 unit test conditions/comments accuracy resolution 12 bits relative accuracy 2 (inl) 1 lsb max differential nonlinearity (dnl) 1 lsb max guaranteed monotonic over temperature zero-scale error 4 mv max offset error 4 mv max measured at code 32 in the linear region offset error tc 5 v/c typ gain error 0.024 % fsr max at 25c 0.06 % fsr max t min to t max gain temperature coefficient 3 2 ppm fsr/c typ dc crosstalk 3 0.5 lsb max reference input/output reference input 3 reference input voltage 2.5 v 1% for specified performance, av dd = 2 refin + 50 mv dc input impedance 1 m? min typically 100 m? input current 10 a max typically 30 na reference range 1 to v dd /2 v min/max reference output 4 enabled via cr8 in the ad5383 control register. cr10 selects the reference voltage. output voltage 2.495/2.505 v min/max at ambient. optimized for 2.5 v operation. cr10 = 1 1.22/1.28 v min/max 1.25 v reference selected. cr10 = 0 reference tc 10 ppm/c typ output characteristics 3 output voltage range 2 0/av dd v min/max short-circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l = 5 k? 1000 pf max dc output impedance 0.5 ? max monitor pin output impedance 500 ? typ three-state leakage current 100 na typ logic inputs (except sda/scl) 3 dv dd = 2.7 v to 5.5 v v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 10 a max total for all pins. t a = t min to t max pin capacitance 10 pf max logic inputs (sda, scl only) v ih , input high voltage 0.7 dv dd v min smbus compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus compatible at dv dd < 3.6 v i in , input leakage current 1 a max v hyst , input hysteresis 0.05 dv dd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering su ppresses noise spikes of less than 50 ns
ad5383 rev. 0 | page 5 of 40 parameter ad5383-5 1 unit test conditions/comments logic outputs (busy , sdo) 3 v ol , output low voltage 0.4 v max dv dd = 5 v 10%, sinking 200 a v oh , output high voltage dv dd C 1 v min dv dd = 5 v 10%, sourcing 200 a v ol , output low voltage 0.4 v max dv dd = 2.7 v to 3.6 v, sinking 200 a v oh , output high voltage dv dd C 0.5 v min dv dd = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a max three-state output capacitance 8 pf typ power requirements av dd 4.5/5.5 v min/max dv dd 2.7/5.5 v min/max power supply sensitivity 3 ?midscale/?v dd C85 db typ ai dd 0.375 ma/channel max outputs unloaded, boost off. 0.25 ma/channel typ 0.475 ma/channel max outputs unloaded, boost on. 0.325 ma/channel typ di dd 1 ma max v ih = dv dd , v il = dgnd. ai dd (power-down) 2 a max typically 200 na di dd (power-down) 20 a max typically 3 a power dissipation 65 mw max outputs unloaded, boost off, av dd = dv dd = 5 v 1 ad5383-5 is calibrated using an external 2.5 v referenc e. temperature range for all versions: C40c to +85c. 2 accuracy guaranteed from v out = 10 mv to av dd C 50 mv. 3 guaranteed by characterization, not production tested. 4 default on the ad5383-5 is 2.5 v. programmable to 1.25 v via cr10 in the ad5383 control register; operating the ad5383-5 with a 1.25 v reference will lead to degraded accuracy specifications.
ad5383 rev. 0 | page 6 of 40 ad5383-3 specifications table 4. av dd = 2.7 v to 3.6 v; dv dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; external refin = 1.25 v; all specifications t min to t max , unless otherwise noted parameter ad5383-3 1 unit test conditions/comments accuracy resolution 12 bits relative accuracy 2 (inl) 1 lsb max differential nonlinearity (dnl) 1 lsb max guaranteed monotonic over temperature zero-scale error 4 mv max offset error 4 mv max measured at code 64 in the linear region offset error tc 5 v/c typ gain error 0.024 % fsr max at 25c 0.06 % fsr max t min to t max gain temperature coefficient 3 2 ppm fsr/c typ dc crosstalk 3 0.5 lsb max reference input/output reference input 3 reference input voltage 1.25 v 1% for specified performance dc input impedance 1 m? min typically 100 m? input current 10 a max typically 30 na reference range 1 to av dd /2 v min/max reference output 4 enabled via cr8 in the ad5383 control register. cr10 selects the reference voltage. output voltage 1.247/1.253 v min/max at ambient. optimized for 1.25 v operation. cr10 = 0 2.43/2.57 v min/max 2.5 v reference enabled. cr10 = 1 reference tc 10 ppm/c typ output characteristics 3 output voltage range 2 0/av dd v min/max short-circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l = 5 k? 1000 pf max dc output impedance 0.5 ? max monitor pin output impedance 500 ? typ three-state leakage current 100 na typ logic inputs (except sda/scl) 3 dv dd = 2.7 v to 3.6 v v ih , input high voltage 2 v min v il, input low voltage 0.8 v max input current 10 a max total for all pins. t a = t min to t max pin capacitance 10 pf max logic inputs (sda, scl only) v ih , input high voltage 0.7 dv dd v min smbus compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus compatible at dv dd < 3.6 v i in , input leakage current 1 a max v hyst , input hysteresis 0.05 dv dd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering su ppresses noise spikes of less than 50 ns
ad5383 rev. 0 | page 7 of 40 parameter ad5383-3 1 unit test conditions/comments logic outputs (busy , sdo) 3 v ol , output low voltage 0.4 v max sinking 200 a v oh , output high voltage dv dd C 0.5 v min sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a max three-state output capacitance 8 pf typ power requirements av dd 2.7/3.6 v min/max dv dd 2.7/5.5 v min/max power supply sensitivity 3 ?midscale/?v dd C85 db typ ai dd 0.375 ma/channel max outputs unloaded, boost off. 0.25 ma/channel typ 0.475 ma/channel max outputs unloaded, boost on. 0.325 ma/channel typ di dd 1 ma max v ih = dv dd , v il = dgnd. ai dd (power-down) 2 a max typically 200 na di dd (power-down) 20 a max typically 3 a power dissipation 39 mw max outputs unloaded, boost off, av dd = dv dd = 3 v 1 ad5383-3 is calibrated using an external 1.25 v re ference. temperature range is C40c to +85c. 2 accuracy guaranteed from v out = 10 mv to av dd C 50 mv. 3 guaranteed by characterization, not production tested. 4 default on the ad5383-3 is 1.25 v. programmable to 2.5 v via cr10 in the ad5383 control register; operating the ad5383-3 with a 2.5 v reference will lead to degraded accuracy specifications and limited input code range. ac characteristics 1 table 5. av dd = 4.5 v to 5.5 v; dv dd = 2.7 v to 5.5 v; agnd = dgnd= 0 v parameter all unit test conditions/comments dynamic performance output voltage settling time 2 1/4 scale to 3/4 scale change settling to 1 lsb. 6 s typ 8 s max slew rate 2 2 v/s typ boost mode off, cr9 = 0 3 v/s typ boost mode on, cr9 = 1 digital-to-analog glitch energy 12 nv-s typ glitch impulse peak amplitude 15 mv typ channel-to-channel isolation 100 db typ see terminology section dac-to-dac crosstalk 1 nv-s typ see terminology section digital crosstalk 0.8 nv-s typ digital feedthrough 0.1 nv-s typ effect of in put bus activity on dac output under test output noise 0.1 hz to 10 hz 15 v p-p typ external reference, midscale loaded to dac 40 v p-p typ internal reference, midscale loaded to dac output noise spectral density @ 1 khz 150 nv/hz typ @ 10 khz 100 nv/hz typ 1 guaranteed by design and characterization, not production tested. 2 the slew rate can be programmed via the current boost control bit (cr9) in the ad5383 control register.
ad5383 rev. 0 | page 8 of 40 timing characteristics serial interface timing table 6. dv dd = 2.7 v to 5.5 v ; av dd = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 4 13 ns min 24th sclk falling edge to sync falling edge t 6 4 33 ns min minimum sync low time t 7 10 ns min minimum sync high time t 7a 50 ns min minimum sync high time in readback mode t 8 5 ns min data setup time t 9 4.5 ns min data hold time t 10 4 30 ns max 24th sclk falling edge to busy falling edge t 11 670 ns max busy pulse width low (single channel update) t 12 4 20 ns min 24th sclk falling edge to ldac falling edge t 13 20 ns min ldac pulse width low t 14 100 ns max busy rising edge to dac output response time t 15 0 ns min busy rising edge to ldac falling edge t 16 100 ns min ldac falling edge to dac output response time t 17 8 s typ dac output settling time, boost mode off t 18 20 ns min clr pulse width low t 19 35 s max clr pulse activation time t 20 5 20 ns max sclk rising edge to sdo valid t 21 5 5 ns min sclk falling edge to sync rising edge t 22 5 8 ns min sync rising edge to sclk rising edge t 23 20 ns min sync rising edge to ldac falling edge 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of v cc ) and are timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, figure 4, and figure 5. 4 standalone mode only. 5 daisy-chain mode only. c l 50pf t o output pin v oh (min) or v ol (max) 200 a 200 a i ol i oh 03731-0-003 figure 2. load circuit for sdo timing diagram (serial interface, daisy-chain mode)
ad5383 rev. 0 | page 9 of 40 1 ldac active during busy 2 ldac active after busy busy sync ldac 1 ldac 2 clr v out v out 2 v out 1 din sclk 03731-0-004 t 7 t 8 t 9 t 4 t 3 t 1 t 2 t 5 t 17 t 17 t 12 t 13 t 18 t 19 t 16 t 14 t 10 t 15 t 13 t 11 t 6 db0 db23 24 24 figure 3. serial interface timing diagram (standalone mode) t 7a 24 48 sclk sync din sdo db23 db0 db23 db0 db23 db0 input word specifies register to be read undefined nop condition selected register data clocked out 03731-0-005 figure 4. serial interface timing diagram (data readback mode) t 22 t 13 t 23 t 21 t 2 t 3 t 20 t 8 t 9 t 7 t 4 t 1 sclk sync sdo din ldac 48 24 db23 db0 db0 db23 db23 db0 input word for dac n input word for dac n+1 undefined input word for dac n 03731-0-006 figure 5. serial interface timing diagram (daisy-chain mode)
ad5383 rev. 0 | page 10 of 40 i 2 c serial interface timing table 7. dv dd = 2.7 v to 5.5 v; av dd = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted parameter 1 , 2 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t hd,dat , data hold time t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 300 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1c b 4 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line 1 guaranteed by design and characterization, not production tested. 2 see figure 6. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of scls falling edge. 4 c b is the total capacitance, in pf, of one bus line. t r and t f are measured between 0.3dv dd and 0.7dv dd . start condition repeated start condition stop condition t 9 t 3 t 1 t 11 t 4 t 10 t 4 t 5 t 7 t 6 t 8 t 2 sda scl 03731-0-007 figure 6. i 2 c compatible serial interface timing diagram
ad5383 rev. 0 | page 11 of 40 parallel interface timing table 8. dv dd = 2.7 v to 5.5 v; av dd = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted parameter 1 , 2 , 3 limit at t min , t max unit description t 0 4.5 ns min reg0, reg1, address to wr rising edge setup time t 1 4.5 ns min reg0, reg1, address to wr rising edge hold time t 2 20 ns min cs pulse width low t 3 20 ns min wr pulse width low t 4 0 ns min cs to wr falling edge setup time t 5 0 ns min wr to cs rising edge hold time t 6 4.5 ns min data to wr rising edge setup time t 7 4.5 ns min data to wr rising edge hold time t 8 20 ns min wr pulse width high t 9 4 700 ns min minimum wr cycle time (single-channel write) t 10 4 30 ns max wr rising edge to busy falling edge t 11 4, 5 670 ns max busy pulse width low (single-channel update) t 12 30 ns min wr rising edge to ldac falling edge t 13 20 ns min ldac pulse width low t 14 100 ns max busy rising edge to dac output response time t 15 20 ns min ldac rising edge to wr rising edge t 16 0 ns min busy rising edge to ldac falling edge t 17 100 ns min ldac falling edge to dac output response time t 18 8 s max dac output settling time t 19 20 ns min clr pulse width low t 20 35 s max clr pulse activation time 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t r = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.2 v. 3 see figure 7. 4 see figure 29. 5 measured with the load circuit of figure 2.
ad5383 rev. 0 | page 12 of 40 t 18 t 18 t 19 t 20 t 13 t 3 t 2 t 8 t 13 t 11 t 9 t 12 t 0 t 1 t 15 t 7 t 6 t 17 t 16 t 10 t 14 t 4 t 5 reg0, reg1, a4..a0 cs wr db11..db0 busy ldac 1 v out 1 v out 2 clr v out ldac 2 1 ldac active during busy 2 ldac active after busy 03731-0-008 f i gure 7. p a r a ll el in ter f a c e t i mi ng d i a g r a m
ad5383 rev. 0 | page 13 of 40 absolute maximum ra tings table 9. t a = 25c, u n less otherwise n o ted 1 p a r a me t e r r a ting av dd t o a g nd C0.3 v t o +7 v dv dd to dgnd C0.3 v to +7 v dig i tal i n puts to dgnd C0.3 v to d v dd + 0.3 v sd a/scl t o dg nd C0.3 v t o + 7 v dig i tal o utputs t o dgnd C0.3 v t o d v dd + 0.3 v refin/refout t o a g nd C0.3 v t o a v dd + 0.3 v a g nd t o dg nd C0.3 v t o +0.3 v vout x t o a g nd C0.3 v t o a v dd + 0.3 v analog i n puts t o a g nd C0.3 v t o a v dd + 0.3 v mon_in i n puts t o a g nd C0.3 v t o a v dd + 0.3 v mon_out t o a g nd C0.3 v t o a v dd + 0.3 v o p era t ing t e mp er a tur e r a nge c o mme r c ia l (b v e rsion) C40c to +85c stor age t e mpera tur e r a nge C65c to +150c j u nc tion t e mpera tur e ( t j m a x) 150c 100-lead l q fp p a ck age ja ther mal i m pedanc e 44c/w r e flo w s o ldering p e ak t e mpera tur e 230c 1 t r ansien t cur r en ts of up t o 100 m a will not cau s e scr la t c h-up s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr osta tic char g e s as high as 4000 v r e adily ac cumula t e on the human body and t e st eq uipmen t and can dis c har g e w i thout det e c t ion. al though this pr oduc t f e atur es pr oprietar y esd pr ot ec tion cir c uitr y , permanen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g e s . ther ef o r e , p r o p er esd pr ecaut i ons a r e r e c o m m ended to a v oid per f or m a nc e degrada t io n or los s of func tionalit y .
ad5383 rev. 0 | page 14 of 40 pin conf igura t ion and fu nction descriptions reset db5 db4 db3 db2 db1 db0 nc nc reg0 reg1 vout23 vout22 vout21 vout20 avdd3 agnd3 dac_gnd3 signal_gnd3 vout19 vout18 vout17 vout16 avdd2 agnd2 59 74 75 69 70 71 72 67 68 66 73 64 65 60 61 62 63 57 58 55 56 53 54 52 51 nc nc nc nc vou t 5 vou t 6 vou t 7 nc nc mo n_ in1 mo n_ in2 mo n_ in3 mo n_ in4 nc mo n_ o u t vou t 8 vou t 9 vou t 10 vou t 11 vou t 12 dac_ gnd2 s i gnal_ g nd2 vou t 13 vou t 14 vou t 15 26 28 27 29 30 32 33 34 35 36 31 37 38 39 40 42 43 44 45 41 46 47 48 49 50 cs /(s y nc/ad0 ) db1 1 / (din/s da) db1 0 / (s clk/s c l) db9/( spi/i2c) db8 db7 db6 s d o(a/b) dv dd dgnd dgnd nc a4 a3 a2 a1 a0 dv dd dv dd dgnd ser /pa r pd wr (dce n/ad1 ) ldac bus y 100 98 99 97 96 95 94 92 91 90 89 88 87 93 86 85 84 82 81 80 79 78 77 76 83 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 24 25 fifo en clr vout24 vout25 vout26 vo u t 2 7 signal_gnd4 dac_gnd4 agnd4 avdd4 vout28 vout29 vout30 vout31 ref gnd refout/refin signal_gnd1 dac_gnd1 avdd1 vout0 vout1 vout2 vout3 vout4 agnd1 pin 1 identifier ad5383 top view (not to scale) 03734-0-002 f i g u re 8. 10 0-l e ad l qfp pin conf ig ur a t ion ta ble 10. pi n f u nct i on des c ri pt i o ns mnemonic f u nc tion vout x buff er ed analog o utputs f o r channel x. each analog output is dr i v en b y a r a i l -to -rail output ampli f ier opera ting a t a gain of 2. each o utput is capable of dr iving an output load of 5 k? to gr ou nd . t y pical output impedanc e is 0.5 ? . signal_gn d(1 C 4) analog gr ound r e f e r e nc e p o in ts f o r each gr oup of eigh t o utput channels . all signal_gnd pins ar e tied t o gether in ter n ally and should be c o nne c ted to the a g nd plane as close as possible to the ad5383. d a c_gnd (1C4) each gr oup of ei gh t channe ls co n t ains a d a c_gnd pin. this is the gr ound r e f e renc e poi n t f o r the in ter n al 12-b i t d a c. these pins shou nd be c o nnec t e d to the a g nd p l ane . a g nd(1C4 ) analog ground r e f e r e nc e p o i n t. each gr oup of e i gh t cha nne ls co n t ains a n a g nd pin. all a g nd pins should be c o nnec t ed ex ter n ally to the a g nd plane . a v dd(1C4 ) analog sup p ly p i ns . each gr ou p of eigh t chann e ls ha s a sep a ra te a v dd pin. the s e pins ar e conn ec ted together in ter n al ly and should be dec o upled with a 0.1 f c e ramic ca pa citor and a 10 f tan t alum capa citor . o p era t ing range f o r the ad5383- 5 is 4.5 v to 5.5 v ; opera ting r a ng e f o r the ad538 3-3 is 2.7 v to 3. 6 v . dgnd gr ound f o r all dig i tal cir c uitr y . dvdd l o g i c p o w e r su pply . guar an tee d oper a ting r a nge is 2.7 v to 5.5 v . i t is r e c o mme nded th a t these pins be decoupled with 0.1 f c e r a mic and 10 f tan t alum capacitors to dgnd . r e f g n d g r o u n d r e fe re n c e p o i n t fo r t h e i n t e r n a l r e fe re n c e. refout/refin the ad5383 c o n t ains a c o mmon refout/refi n pin. w h en the in te r n al r e f e r e nc e is selec t ed , this pin is the r e f e r e nc e output. i f the applica t ion r e q u ir es an ex ter n a l r e f e r e nce , it can b e ap plied to this pin and the in te r n al r e f e r e nc e c a n be disabled via the c o n t r o l r e gister . the default f o r this pin is a r e f e r e nc e i n put.
ad5383 rev. 0 | page 15 of 40 mnemonic function mon_out when the monitor function is enabled, this output acts as the o utput of a 36-to-1 channel multiplexer that can be programmed to multiplex one of channels 0 to 31or any of the monitor input pins (mon_in1 to mon_in4) to the mon_out pin. the mon_out pins output impedance is typi cally 500 ?, and is intended to drive a high input impedance like that exhibited by sar adc inputs. mon_inx mon_in monitor input pins. the ad5383 contains four moni tor input pins that allow the user to connect input signals within the maximum ratings of the device to these pins for monitoring purposes. any of the signals applied to the mon_in pins along with th e 32 output channels can be switched to the mon_out pin via software. an external adc for example can be used to monitor these signals. ser/ par interface select input. this pin allows the user to select whether the serial or parallel interface will be used. if it is ti ed high, the serial interface mode is selected and pin 97 ( spi /i2c) is used to determine if the interface mode is spi or i 2 c. parallel interface mode is selected when ser/ par is low. cs /( sync /ad0) in parallel interface mode, this pin acts as chip sele ct input (level sensitive, active low). when low, the ad5383 is selected. serial interface mode. this is the frame synchronization input signal for the serial clocks before the addressed register is updated. i 2 c mode. this pin acts as a hardware address pin used in conjunction with ad1 to determine the software address for the device on the i 2 c bus. wr /(dcen/ ad1) multifunction pin. in parallel interface mode, this pin acts as write enable. in serial interface mode, this pin acts as a daisy-chain enable in spi mode and as a hardware address pin in i 2 c mode. parallel interface write input (edge sensitive). the rising edge of wr is used in conjunction with cs low and the address bus inputs to write to the selected device registers. serial interface. daisy-chain select input (level sensitive, ac tive high). when high, this si gnal is used in conjunction with ser/ par high to enable the spi serial interface daisy-chain mode. i 2 c mode. this pin acts as a hardware address pin used in conjunction with ad0 to determine the software address for this device on the i 2 c bus. db11Cdb0 parallel data bus. db11 is the msb and db 0 is the lsb of the input data-word on the ad5383. a4Ca0 parallel address inputs. a5 to a0 are decoded to addre ss one of the ad5383s 40 input channels. used in conjunction with the reg1 and reg0 pins to determine the destination register for the input data. reg1, reg0 in parallel interface mode reg1 and reg0 are used in deco ding the destination registers for the input data. reg1 and reg0 are decoded to address the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registers. sdo/( a /b) serial data output in serial interface mode. three-stateable cmos output. sdo can be used for daisy-chaining a number of devices together. data is clocked out on sdo on the rising edge of sclk, and is valid on the falling edge of sclk. when operating in parallel interface mode, this pin acts as the a or b data register select when writing data to the ad5383s data registers with toggle mode selected (see th e toggle mode function section). in toggle mode, the ldac is used to switch the output between the data cont ained in the a and b data registers. all dac channels contain two data registers. in normal mode, data register a is the default for data transfers. busy digital cmos output. busy goes low during internal calc ulations of the data (x2) loaded to the dac data register. during this time, the user can continue writing new data to the x1, c, and m registers in parallel mode (these are stored in a fifo), but no further updates to the dac registers and dac outputs can take place. if ldac is taken low while busy is low, this event is stored. busy also goes low during power-on reset, and when the busy pin is low. during this time, the interface is disabled and any events on ldac are ignored. a clr operation also brings busy low. ldac load dac logic input (active low). if ldac is taken low while busy is inactive (high), the contents of the input registers are transferred to the dac registers and the dac outputs are updated. if ldac is taken low while busy is active and internal calculations are taking place, the ldac event is stored and the dac registers are updated when busy goes inactive. however any events on ldac during power-on reset or on reset are ignored. clr asynchronous clear input. the clr input is falling edge sensitive. when clr is activated, all channels are updated with the data contained in the clr code register. busy is low for a duration of 35 s while all channels are being updated with the clr code. reset asynchronous digital reset input (falling edge sensitive). the function of this pin is equivalent to that of the power- on reset generator. when this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. this sequence typically takes 270 s. the falling edge of reset initiates the reset process and busy goes low for the duration, returning high when reset is complete. while busy is low, all interfaces are disabled and all ldac pulses are ignored. when busy returns high, the part resumes normal operation and the status of the reset pin is ignored until the next falling edge is detected.
ad5383 rev. 0 | page 16 of 40 mnemonic function pd power down (level sensitive, active hi gh). pd is used to place the device in low power mode where the device consumes 2 a analog supply current and 20 a digital su pply current. in power-down mode, all internal analog circuitry is placed in low power mode, and the analog output will be configured as a high impedance output or will provide a 100 k? load to ground, depending on how the power-down mode is configured. the serial interface remains active during power-down. fifoen fifo enable (level sensitive, active hi gh). when connected to dvdd, the internal fifo is enabled, allowing the user to write to the device at full speed. fifo is only availabl e in parallel interface mode. the status of the fifo_en pin is sampled on power-up, and also following a clear or reset, to determine if the fifo is enabled. in either serial or i 2 c interface modes, the fifo_en pin should be tied low. db9 ( spi /i2c) multifunction input pin. in parallel interface mode, this pin acts as db9 of the paralle l input data-word. in serial interface mode, this pin acts as serial interface mode select. when serial interface mode is selected (ser/ par = 1) and this input is low, spi mode is selected. in spi mode, db12 is the serial clock (sclk) input and db11 is the serial data (din) input. when serial interface mode is selected (ser/ par = 1) and this input is high i2c mode is selected. in this mode, db12 is the serial clock (scl) input and db11 is the seri al data (sda) input. db10 (sclk/scl) multifunction input pin. in parallel interface mode, this pi n acts as db10 of the parallel input data-word. in serial interface mode, this pin acts as a serial clock input. serial interface mode. in serial interface mode, data is clocke d into the shift register on the falling edge of sclk. this operates at clock speeds up to 50 mhz. i 2 c mode. in i 2 c mode, this pin performs the scl function, clocking data into the device. the data transfer rate in i 2 c mode is compatible with both 100 khz and 400 khz operating modes. db11/(din/sda) multifunction data input pin. in parallel interfac e mode, this pin acts as db11 of the parallel input data-word . serial interface mode. in serial interface mode, this pin acts as the serial data input. data must be valid on the falling edge of sclk. i 2 c mode. in i 2 c mode, this pin is the serial data pin (s da) operating as an open-drain input/output. nc no connect. the user is advised not to connect any signal to these pins.
ad5383 rev. 0 | page 17 of 40 terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error, and is expressed in lsb. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. ideally, with all 0s loaded to the dac and m = all 1s, c = 2 n C 1 vout ( zero-scale ) = 0 v zero-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in mv. it is mainly due to offsets in the output amplifier. offset error offset error is a measure of the difference between vout (actual) and vout (ideal) in the linear region of the transfer function, expressed in mv. offset error is measured on the ad5383-5 with code 32 loaded into the dac register, and on the ad5383-3 with code 64. gain error gain error is specified in the linear region of the output range between v out = 10 mv and v out = av dd C 50 mv. it is the deviation in slope of the dac transfer characteristic from the ideal and is expressed in %fsr with the dac output unloaded. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other dacs. it is expressed in lsb. dc output impedance this is the effective output source resistance. it is dominated by package lead resistance. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full-scale input change, and is measured from the busy rising edge. digital-to-analog glitch energy this is the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x1fff and 0x2000. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one dac due to both the digital change and to the subsequent analog output change at another dac. the victim channel is loaded with midscale. dac-to-dac crosstalk is specified in nv-s. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter is defined as the digital crosstalk and is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density this is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hertz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/hz in a 1 hz bandwidth at 10 khz.
ad5383 rev. 0 | page 18 of 40 typical perf orm ance cha r acte ristics 03732-0-017 input code 4096 0 512 1024 1536 2048 2560 3072 3584 inl e rror (ls b ) 1.00 0.75 0.50 0.25 0 ? 0.25 ? 0.50 ? 0.75 ? 1.00 av dd = 5v refin = 2.5v t a = 25c f i gure 9. t y pic a l a d 5383-5 i n l p l ot 03731-0-034 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amp l itude (v ) 2.523 2.539 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 av dd = dv dd = 5v v ref = 2.5v t a = 25c 14ns/sample number 1 lsb change around midscale glitch impulse = 10nv-s f i gur e 1 0 . ad53 83 -5 gli t c h im pul s e 03732-0-003 av dd = dv dd = 5v v ref = 2.5v t a = 25c v out f i gure 1 1 . slew ra te wi th boo s t o ff 03732-0-018 input code 4096 0 512 1024 1536 2048 2560 3072 3584 inl e rror (ls b ) 1.00 0.75 0.50 0.25 0 ? 0.25 ? 0.50 ? 0.75 ? 1.00 av dd = 3v refin = 1.25v t a = 25c f i g u re 12. t y pic a l a d 53 8 3 -3 i n l p l ot 03731-0-036 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amp l itude (v ) 1.245 1.254 1.253 1.252 1.251 1.250 1.249 1.248 1.247 1.246 av dd = dv dd = 3v v ref = 1.25v t a = 25c 14ns/sample number 1 lsb change around midscale glitch impulse = 5nv-s f i gur e 1 3 . ad53 83 -3 gli t c h im pul s e 03732-0-004 av dd = dv dd = 5v v ref = 2.5v t a = 25c v out f i gure 1 4 . slew ra te wi th boo s t o n
ad5383 rev. 0 | page 19 of 40 04598-0-049 ai dd (ma) 11 89 1 0 p e rce ntage of units (%) 14 12 10 8 6 4 2 av dd = 5.5v v ref = 2.5v t a = 25c f i g u re 15. a i dd hi st o g r a m 04598-0-050 di dd (ma) 0.8 0.9 0.4 0.5 0.6 0.7 numbe r of units 0 10 8 6 4 2 dv dd = 5.5v v ih = dv dd v il = dgnd t a = 25c f i g u re 16. di dd his t og r a m 03731-0-045 av dd = dv dd = 5v v ref = 2.5v t a = 25 c exits soft pd to midscale v out busy wr f i g u re 17. e x it ing s o f t p o we r - d o wn 03731-0-011 av dd = dv dd = 5v v ref = 2.5v t a = 25c power supply ramp rate = 10ms v out av dd f i gur e 1 8 . ad53 83 p o w e r - up t r a n sie n t 03731-0-048 reference drift (ppm/ c) ?5.0 ?1.5 2.5 ?3.5 ?4.5 ?4.0 0.5 ? 0.5 3.5 ?2.5 1.5 ?1.0 3.0 ? 3.0 1.0 0 4.0 5.0 4.5 ?2.0 2.0 fre q ue ncy 0 40 30 20 35 25 15 10 5 f i gure 19. a d 5 3 8 3 r e fout t e mper at ur e coeffi ci ent 03731-0-038 av dd = dv dd = 5v v ref = 2.5v t a = 25c exits hardware pd to midscale pd v out f i g u re 20. e x it ing h a r d ware p o we r - d o wn
ad5383 rev. 0 | page 20 of 40 03731-0-039 current (ma) ? 4 0 ? 20 ?10 ? 5 ? 2 0 2 5 10 20 40 v out (v ) ?1 6 4 3 2 5 1 0 zeroscale 1/4 scale midscale 3/4 scale fullscale av dd = dv dd = 5v v ref = 2.5v t a = 25c f i g u re 21. a d 5 3 8 3 - 5 o u t p ut a m p lif i e r s o u r c e and si nk ca pabi lit y 03731-0-047 i source /i sink (ma) 2.00 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 e rror v o ltage (v ) ? 0.20 0.20 0.10 0.05 0.15 0 ? 0.05 ? 0.10 ? 0.15 av dd = 5v v ref = 2.5v t a = 25 c error at zero sinking current (v dd ?v out ) at full-scale sourcing current f i g u re 22. h e ad r o o m at ra ils v s . s o u r ce/s i nk cur r e n t 03731-0-047 frequency (hz) 100k 100 1k 10k outp ut nois e (nv / hz) 0 600 500 400 300 200 100 av dd = 5v t a = 25c refout decoupled with 100nf capacitor refout = 2.5v refout = 1.25v f i g u re 23. r e fou t nois e spe c t r a l d e n s it y 03731-0-040 current (ma) ? 4 0 ? 20 ?10 ? 5 ? 2 0 2 5 10 20 ?40 v out (v ) ?1 6 4 3 2 5 1 0 zero-scale 1/4 scale midscale 3/4 scale full-scale av dd = dv dd = 3v v ref = 1.25v t a = 25c f i g u re 24. a d 5 3 8 3 - 3 o u t p ut a m p lif i e r s o u r c e and si nk ca pabi lit y 03731-0-041 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amp l itude (v ) 2.449 2.456 2.455 2.454 2.453 2.452 2.451 2.450 av dd = dv dd = 5v v ref = 2.5v t a = 25c 14ns/sample number f i gure 25. a d jac e nt chann e l d a c-to -da c cr osstalk av dd = dv dd = 5v v ref = 2.5v t a = 25c exits soft pd to midscale 03731-0-046 av dd = dv dd = 5v t a = 25c dac loaded with midscale external reference y axis = 5 v/div x axis = 100ms/div f i g u re 26. 0. 1 h z t o 10 h z no is e plot
ad5383 rev. 0 | page 21 of 40 functional description d a c architec ture g ener al the ad5383 is a co m p lete , sin g le-s u p p l y , 32-c h a nne l v o l t a g e output d a c t h at of f e r s 1 2 - bit re s o lut i on . t h e p a r t i s a v ai l a bl e i n a 100-lead l q fp p a c k a g e an d fea t ur es bo th a p a ral l e l a nd a se ri al i n t e rf a c e . t h i s p r o d u c t in c l u d e s a n in t e rn al , so ft w a r e s e lec t a b le , 1.25 v/2.5 v , 10 p p m/c r e f e r e n c e tha t c a n be us e d to dr i v e t h e b u f f er e d r e fer e n c e in pu ts; al t e r n a t i v e l y , a n ext e r n al r e fer e n c e can b e us e d t o dr i v e t h es e in pu ts. i n t e r n al/ext er nal re f e re nc e s e l e c t i o n i s v i a t h e c r 8 bit i n t h e c o n t ro l re g i ste r ; cr10 s e le c t s t h e r e fer e n c e ma g n i t ude if t h e i n ter n al r e fer e n c e is s e le c t e d . al l c h anne ls ha v e a n on-c hi p o u t p u t am p l if ier wi th ra il- t o- ra il o u t p u t ca pa b l e o f d r i v in g 5 k ? in pa ralle l w i t h a 200 pf lo ad . 03732-0-005 v out r r 12-bit dac dac reg m reg c reg 1 input reg 2 input dat a v ref avdd f i gure 27. sing le - c hann el a r ch ite c t ure t h e arch ite c tu re of a s i ng l e d a c ch an nel c o ns i s t s of a 1 2 - b i t re s i stor - s t r i n g d a c f o l l owe d by an output bu f f e r am pl i f i e r op e r a t i n g at a g a i n of 2 . t h i s re s i stor - s t r i n g arc h ite c tu re gua r a n te es d a c m o n o t o nici ty . the 12- b i t b i nar y dig i t a l co de lo aded t o the d a c r e g i s t er det e r m in es a t wha t n o de o n t h e s t ri n g th e v o l t a g e i s ta p p e d o f f be f o r e be i n g f e d t o th e o u t p u t am pl i f i e r . e a ch ch an nel o n t h e s e d e v i c e s c o n t a i ns i n d e p e nd e n t o f fs et a n d gain co n t r o l r e g i s t ers t h a t al lo w t h e u s er t o dig i t a l l y t r im o f fs et a nd ga in. th es e reg i s t ers g i v e t h e us er t h e ab i l i t y t o ca lib r a t e o u t er r o rs in t h e co m p let e sig n a l cha i n , in cl ud in g t h e d a c, usin g t h e in t e r n a l m an d c r e g i st ers, w h ich h o l d t h e co r r e c tio n fac t ors. al l c h a nne ls a r e do u b le b u f f er e d , al lo win g s y nc h r onou s up d a t i ng of a l l ch a n n e l s u s i n g t h e ld a c pi n . f i gur e 27 sh o w s a b l o c k di a g ram o f a sin g le ch a nnel on t h e ad5383. th e dig i tal in p u t tran sf er f u n c tio n f o r eac h d a c can be r e p r e s en t e d a s x2 = [( m + 2)/ 2 n x1 ] + ( c C 2 n C 1 ) w h er e: x2 = th e da ta- w o r d loa d ed t o t h e r e si s t o r s t ri n g d a c . x1 = t h e 12 -b i t da t a -w o r d wr i t ten t o t h e d a c i n p u t r e g i st er . m = t h e gain co ef f i cien t (defa u l t is 0xffe). th e ga in co ef f i cien t is wr i t t e n t o the 11 m o s t sig n if ica n t b i ts (d b11 t o d b 1) a nd the ls b (d b0) is 0. n = d a c r e so l u tio n ( n = 12 f o r ad5383). c is the12-b i t o f fs et co ef f i cien t ( d efa u l t is 0x800 ). the co m p le t e t r a n sfer f u n c t i o n fo r t h es e de vi ces ca n b e r e p r es en t e d as v ou t = 2 v ref x2 /2 n x2 is th e da t a -wo r d lo aded t o t h e r e sis t o r s t r i n g d a c. v ref is t h e in t e r n al r e fer e nce v o l t a g e o r t h e r e fer e n c e v o l t a g e ext e r n al l y a p plie d t o t h e d a c refout /r efin p i n. f o r sp e c if ie d p e r f o r ma n c e , an ext e r n al r e fer e n c e v o l t a g e o f 2.5 v is r e co mmen d e d f o r th e ad5380-5 a nd 1.25 v f o r th e ad5380-3 . d a t a dec o ding the ad5383 con t a i n s a 12 -b i t da ta b u s, d b 11Cd b 0. dep e n d in g o n t h e val u e o f reg1 an d re g 0 (s e e t a b l e 11), t h is da t a is lo ade d in to t h e addr ess e d d a c in p u t r e g i sters, o f fs et (c) r e g i s t ers, o r ga in (m) r e g i s t ers. the fo r m a t da t a , o f fs et (c), a n d ga in (m) r e g i st e r co n t en ts a r e sh o w n i n t a b l e 1 2 t o t a b l e 14. table 11. register selection reg1 reg0 regist er s e lec t ed 1 1 i n put da ta r e g i ster (x1) 1 0 o f f s et r e g i ster (c) 0 1 g a in r e g i ster (m) 0 0 special f u nc tio n r e gisters ( s frs) table 12. dac data format (reg1 1, reg 0 1) db11 t o db0 d a c o u tput ( v ) 1 1 1 1 1 1 1 1 1 1 1 1 2 v ref (4095/4096) 1 1 1 1 1 1 1 1 1 1 1 0 2 v ref (4094/4096) 1 0 0 0 0 0 0 0 0 0 0 1 2 v ref (2049/4096) 1 0 0 0 0 0 0 0 0 0 0 0 2 v ref (2048/4096) 0 1 1 1 1 1 1 1 1 1 1 1 2 v ref (2047/4096) 0 0 0 0 0 0 0 0 0 0 0 1 2 v ref (1/4096) 0 0 0 0 0 0 0 0 0 0 0 0 0 table 13. offse t data format (reg1 1, re g0 0) db11 t o db0 o f f s et (lsb) 1 1 1 1 1 1 1 1 1 1 1 1 + 2 0 4 8 1 1 1 1 1 1 1 1 1 1 1 0 + 2 0 4 7 1 0 0 0 0 0 0 0 0 0 0 1 + 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 C 1 0 0 0 0 0 0 0 0 0 0 0 1 C 2 0 4 7 0 0 0 0 0 0 0 0 0 0 0 0 C 2 0 4 8 table 14. gain data format (reg1 0, reg 0 1) db11 t o db1 g a in f a c t or 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 . 7 5 0 1 1 1 1 1 1 1 1 1 1 0 0 . 5 0 0 1 1 1 1 1 1 1 1 1 0 0 . 2 5 0 0 0 0 0 0 0 0 0 0 0 0 0
ad5383 rev. 0 | page 22 of 40 on-chip special function registers (sfr) the ad5383 contains a number of special function registers (sfrs), as outlined in table 15. sfrs are addressed with reg1 = reg0 = 0 and are decoded using address bits a4 to a0. table 15. sfr register functions (reg1 = 0, reg0 = 0) r/ w a4 a3 a2 a1 a0 function x 0 0 0 0 0 nop (no operation) 0 0 0 0 0 1 write clr code 0 0 0 0 1 0 soft clr 0 0 1 0 0 0 soft power-down 0 0 1 0 0 1 soft power-up 0 0 1 1 0 0 control register write 1 0 1 1 0 0 control register read 0 0 1 0 1 0 monitor channel 0 0 1 1 1 1 soft reset sfr commands nop (no operation) reg1 = reg0 = 0, a4Ca0 = 00000 performs no operation but is useful in serial readback mode to clock out data on d out for diagnostic purposes. busy pulses low during a nop operation. write clr code reg1 = reg0 = 0, a4Ca0 = 00001 db11Cdb0 = contain the clr data bringing the clr line low or exercising the soft clear function will load the contents of the dac registers with the data con- tained in the user configurable clr register, and will set vout0 to vout31 accordingly. this can be very useful for setting up a specific output voltage in a clear condition. it is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hard- ware or software clear to load this code to all dacs, removing the need for individual writes to each dac. default on power- up is all zeros. soft clr reg1 = reg0 = 0, a4Ca0 = 00010 db11Cdb0 = dont care executing this instruction performs the clr, which is function- ally the same as that provided by the external clr pin. the dac outputs are loaded with the data in the clr code register. it takes 35 s to fully execute the soft clr, as indicated by the busy low time. soft power-down reg1 = reg0 = 0, a4Ca0 = 01000 db11Cdb0 = dont care executing this instruction performs a global power-down feature that puts all channels into a low power mode that reduces the analog supply current to 2 a max, and the digital current to 20 a. in power-down mode, the output amplifier can be configured as a high impedance output or provide a 100 k? load to ground. the contents of all internal registers are retained in power-down mode. no register can be written to while in power-down. soft power-up reg1 = reg0 = 0, a4Ca0 = 01001 db11Cdb0 = dont care this instruction is used to power up the output amplifiers and the internal reference. the time to exit powerCdown is 8 s. the hardware power-down and software function are internally combined in a digital or function. soft reset reg1 = reg0 = 0, a4Ca0 = 01111 db11Cdb0 = dont care this instruction is used to implement a software reset. all internal registers are reset to their default values, which correspond to m at full scale and c at zero. the contents of the dac registers are cleared, setting all analog outputs to 0 v. the soft reset activation time is 135 s.
ad5383 rev. 0 | page 23 of 40 table 16. control register contents msb lsb cr11 cr10 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 control register write/read reg1 = reg0 = 0, a4Ca0 = 01100, r/ w status determines if the operation is a write (r/ w = 0) or a read (r/ w = 1). db11 to db0 contains the control register data. control register contents cr11: power-down status. this bit is used to configure the output amplifier state in power down. cr11 = 1. amplifier output is high impedance (default on power-up). cr11 = 0. amplifier output is 100 k? to ground. cr10: ref select. this bit selects the operating internal reference for the ad5383. cr12 is programmed as follows: cr10 = 1: internal reference is 2.5 v (ad5383-5 default), the recommended operating reference for ad5383-5. cr10 = 0: internal reference is 1.25 v (ad5383-3 default), the recommended operating reference for ad5383-3. cr9: current boost control. this bit is used to boost the current in the output amplifier, thereby altering its slew rate. this bit is configured as follows: cr9 = 1: boost mode on. this maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. cr9 = 0: boost mode off (default on power-up). this reduces the bias current in the output amplifier and reduces the overall power consumption. cr8: internal/external reference. this bit determines if the dac uses its internal reference or an externally applied reference. cr8 = 1: internal reference enabled. the reference output depends on data loaded to cr10. cr8 = 0: external reference selected (default on power up). cr7: channel monitor enable (see channel monitor function) cr7= 1: monitor enabled. this enables the channel monitor function. after a write to the monitor channel in the sfr register, the selected channel output is routed to the mon_out pin. cr7 = 0: monitor disabled (default on power-up). when the monitor is disabled, the mon_out pin is tristated. cr6: thermal monitor function. this function is used to monitor the ad5383s internal die temperature when enabled. the thermal monitor powers down the output amplifiers when the temperature exceeds 130c. th is function can be used to protect the device in cases where power dissipation may be exceeded if a number of output channels are simultaneously short-circuited. a soft power-up will re-enable the output amplifiers if the die temperature has dropped below 130c. cr6 = 1: thermal monitor enabled. cr6 = 0: thermal monitor disabled (default on power- up). cr5 and cr4: dont care. cr3 to cr0: toggle function enable. this function allows the user to toggle the output between two codes loaded to the a and b register for each dac. control register bits cr3 to cr0 are used to enable individual groups of eight channels for opera- tion in toggle mode. a logic 1 written to any bit enables a group of channels; a logic 0 disables a group. ldac is used to toggle between the two registers. logic 1 enables a group of channels; logic 0 disables a group of channels. table 17. cr bit group channels cr3 3 24C31 cr2 2 16C23 cr1 1 8C15 cr0 0 0C7 channel monitor function reg1 = reg0 = 0, a4Ca0 = 01010 db11Cdb6 = contain data to address the monitored channel. a channel monitor function is provided on the ad5383. this feature, which consists of a multiplexer addressed via the interface, allows any channel output or signals connected to the mon_in pins to be routed to the mon_out pin for monitoring using an external adc. the channel monitor function must be enabled in the control register before any channels are routed to mon_out. on the ad5383, db11 to db6 contain the channel address for the monitored channel. selecting channel address 63 three-states mon_out.
ad5383 rev. 0 | page 24 of 40 table 18. a d 5 383 channel monitor deco ding r e g 1 r e g 0 a 4 a 3 a 2 a 1 a 0 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 C d b 0 m o n _ o u t 0 0 0 1 0 1 0 0 0 0 0 0 0 x v o u t 0 0 0 0 1 0 1 0 0 0 0 0 0 1 x v o u t 1 0 0 0 1 0 1 0 0 0 0 0 1 0 x v o u t 2 0 0 0 1 0 1 0 0 0 0 0 1 1 x v o u t 3 0 0 0 1 0 1 0 0 0 0 1 0 0 x v o u t 4 0 0 0 1 0 1 0 0 0 0 1 0 1 x v o u t 5 0 0 0 1 0 1 0 0 0 0 1 1 0 x v o u t 6 0 0 0 1 0 1 0 0 0 0 1 1 1 x v o u t 7 0 0 0 1 0 1 0 0 0 1 0 0 0 x v o u t 8 0 0 0 1 0 1 0 0 0 1 0 0 1 x v o u t 9 0 0 0 1 0 1 0 0 0 1 0 1 0 x vout1 0 0 0 0 1 0 1 0 0 0 1 0 1 1 x vout1 1 0 0 0 1 0 1 0 0 0 1 1 0 0 x vout1 2 0 0 0 1 0 1 0 0 0 1 1 0 1 x vout1 3 0 0 0 1 0 1 0 0 0 1 1 1 0 x vout1 4 0 0 0 1 0 1 0 0 0 1 1 1 1 x vout1 5 0 0 0 1 0 1 0 0 1 0 0 0 0 x vout1 6 0 0 0 1 0 1 0 0 1 0 0 0 1 x vout1 7 0 0 0 1 0 1 0 0 1 0 0 1 0 x vout1 8 0 0 0 1 0 1 0 0 1 0 0 1 1 x vout1 9 0 0 0 1 0 1 0 0 1 0 1 0 0 x vout2 0 0 0 0 1 0 1 0 0 1 0 1 0 1 x vout2 1 0 0 0 1 0 1 0 0 1 0 1 1 0 x vout2 2 0 0 0 1 0 1 0 0 1 0 1 1 1 x vout2 3 0 0 0 1 0 1 0 0 1 1 0 0 0 x vout2 4 0 0 0 1 0 1 0 0 1 1 0 0 1 x vout2 5 0 0 0 1 0 1 0 0 1 1 0 1 0 x vout2 6 0 0 0 1 0 1 0 0 1 1 0 1 1 x vout2 7 0 0 0 1 0 1 0 0 1 1 1 0 0 x vout2 8 0 0 0 1 0 1 0 0 1 1 1 0 1 x vout2 9 0 0 0 1 0 1 0 0 1 1 1 1 0 x vout3 0 0 0 0 1 0 1 0 0 1 1 1 1 1 x vout3 1 0 0 0 1 0 1 0 1 0 0 0 0 0 x mon _ in 1 0 0 0 1 0 1 0 1 0 0 0 0 1 x mon _ in 2 0 0 0 1 0 1 0 1 0 0 1 0 x mon _ in 3 0 0 0 1 0 0 1 0 0 0 1 1 x mon _ in 4 0 0 0 1 0 1 0 1 0 0 1 0 0 x u n d e f i n e d 0 0 0 1 0 1 0 1 0 0 1 0 1 x u n d e f i n e d ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 1 0 1 0 1 1 1 1 1 0 x u n d e f i n e d 0 0 0 1 0 1 0 1 1 1 1 1 1 x t h r e e - sta t e 03734-0-003 db11 ?db6 channel address ad5383 channel monitor decoding 00 010 10 vout0 vout1 vout31 vout30 mon_out reg1 reg0 a4 a3 a2 a1 a0 mon_in1 mon_in2 mon_in3 mon_in4 f i gure 28. channe l monitor d ecoding
ad5383 rev. 0 | page 25 of 40 hardw a re functions rese t func tio n br ing i ng t h e res e t lin e lo w r e s e ts t h e co n t e n ts o f al l in t e r n al re g i ste r s to t h e i r p o we r - on re s e t st ate. r e s e t i s a ne g a t i v e e d ge - s e n s i t i v e i n p u t. the def a u l t co r r es p o n d s t o m a t f u l l s c ale an d to c a t zer o . the con t e n ts o f t h e d a c r e g i s t ers a r e cle a r e d , s e t t in g v o ut 0 t o v o ut 31 t o 0 v . this s e q u en ce t a k e s 270 s max. the fa l l in g e d ge o f res e t ini t i a t e s t h e r e s e t p r o c es s; bu s y go e s lo w f o r th e d u ra tio n , r e t u r n in g high when res e t is co m p let e . wh i l e bu s y is lo w , a l l in t e r f aces a r e d i s a b l e d and a l l l d a c pu l s e s are i g nor e d. whe n bu s y re tu r n s h i g h , t h e p a r t re su me s n o r m al o p er a t i o n an d t h e s t a t u s o f t h e res e t p i n is i g n o r e d un t i l t h e n e xt fa l l in g e d ge is dete c t e d . asy n chronous clear func tion br ing i ng t h e clr lin e lo w c l ea rs the co n t en ts o f t h e d a c r e g i s t ers t o t h e da t a con t ai n e d i n t h e us er co nf i g ura b le clr r e g i s t er an d s e ts v o ut 0 t o v o ut 31 acco r d ing l y . this f u n c - t i o n can b e us e d in sy ste m ca l i b r a t ion to lo ad zer o s c a l e and f u l l s c ale t o al l cha n n e ls. the exe c u t io n t i m e fo r a c l r is 32 s. busy and ld a c fu nc tio n s bu s y is a dig i tal cmos o u t p u t tha t in dic a t e s t h e sta t us o f th e ad5383. th e va l u e o f x2, th e in ter n al da ta lo ade d t o the d a c da t a r e g i s t er , is calc u l a t e d e a ch t i me t h e us er w r i t es ne w da t a to t h e co r r es p o n d i n g x1, c, o r m r e g i s t ers. d u r i n g t h e calc u l a t ion of x 2 , t h e bu s y o u t p u t g o es lo w . w h ile bu s y is lo w , t h e us er ca n con t i n ue wr i t in g ne w d a t a to t h e x 1 , m, o r c r e g i sters, b u t no da c o u t p u t u p d a t e s c a n t a k e p l a c e . t h e da c o u t p u t s a r e u p da t e d b y tak i n g th e ld a c in pu t lo w . i f ld a c g o es lo w w h i l e bu s y i s a c ti v e , th e ld a c ev e n t i s s t o r ed a n d th e d a c o u t p u t s u p da te i m m e dia t e l y a f t e r bu s y g o es hig h . th e us er ma y h o ld th e ld a c in p u t pe rm a n en tl y lo w , i n wh i c h case th e d a c o u t p u t s u p da t e i m m e dia t e l y a f ter bu s y go e s hig h . bu s y al so g o e s l o w d u ri n g po w e r - o n r e se t a n d w h en a fall in g ed g e i s dete c t e d on t h e res e t p i n . duri n g th is ti m e , all i n t e rfa c e s a r e dis a b l e d an d an y e v en ts on ld a c a r e ig n o r e d . th e ad5383 co n t a i n s an ext r a fe a t ur e w h er eb y a d a c r e g i s t er is n o t up da te d unles s i t s x2 r e g i s t er has be e n wr i t t e n t o sin c e t h e las t t i m e ld a c was b r o u g h t lo w . n o r m a l ly , w h en ld a c is b r o u g h t lo w , t h e d a c r e g i s t e r s a r e f i l l e d wi t h t h e con t e n ts o f t h e x2 r e g i s t ers. h o w e v e r , th e ad5383 wil l onl y u p da te the d a c r e g i s t er if the x 2 d a t a h a s ch a n ge d, t h e r e b y re mov i ng u n ne c e ss ar y d i g i t a l c r o sst a l k. f i fo oper a t ion in p a r a llel mode the ad5383 con t a i n s a fifo to o p timize o p era t io n w h en o p era t i n g i n p a ral l e l in ter f ace mo de . th e fifo ena b le (le v el s e n s i t i v e , ac t i v e hig h ) is us e d t o ena b le t h e i n t e r n al fifo . w h en co nnec t e d t o d v d d , th e in t e r n al fifo is ena b led , al lo win g t h e us er t o wr i t e t o t h e de vice a t f u l l s p e e d . fifo is o n l y a v a i la b l e in p a ral l e l in t e r f ac e m o de . th e s t a t us o f t h e fifo _en p i n is s a m p le d o n p o w e r - u p , and a f te r a clr or res e t , to de te r m i n e if th e fifo is ena b led . i n ei t h er s e r i al o r i 2 c in t e r f ace mo des, fifo_en sh o u ld b e tie d lo w . u p t o 128 s u cces s i v e ins t r u c t io n s ca n b e wr i t te n to t h e f i f o a t m a x i m u m sp e e d i n p a r a l l el m o de. w h en t h e fifo is f u l l , a n y f u r t h e r wr i t es t o t h e de vic e a r e ig n o r e d . f i gur e 29 s h o w s a com p a r is o n betw een fifo m o de a nd n o n - f i f o m o d e i n ter m s o f cha nnel u p d a te t i m e . f i gur e 2 9 also o u tli n e s digi tal loa d i n g t i m e . number of writes time ( s) 1 4 7 10 13 16 19 22 25 28 31 34 37 0 10 5 15 25 20 40 without fifo (channel update time) with fifo (channel update time) with fifo (digital loading time) 03731-0-018 f i gure 29. channe l up date rate (fif o vs. non-fif o ) po wer- on reset the ad5383 con t a i n s a p o w e r - o n r e s e t g e n e ra to r a n d s t a t e m a c h in e . th e p o w e r - o n r e se t r e se t s all r e gi s t e r s t o a p r ed e f in e d s t a t e and co nf ig ur es t h e a n alog o u t p uts as hig h im p e dan c e . the bu s y pi n go e s l o w du r i ng t h e p o we r - on re s e t s e qu e n c i ng , p r e v en t i n g da t a wr i t es t o t h e de vice . po wer-down the ad5383 con t a i n s a g l obal p o w e r - do wn f e a t ur e tha t p u ts al l c h a n n e ls in t o a lo w p o w e r m o de a nd r e d u ces th e analog p o w e r co n s um p t io n to 2 a max an d dig i t a l p o w e r co n s um pt io n to 20 a max . i n p o w e r - do wn m o de, t h e o u t p u t am plif ier can b e co nf igur ed as a hig h im p e dan c e o u t p u t o r p r o v ide a 100 k? lo ad t o g r o u n d . the co n t en ts o f al l in t e r n al r e g i st ers a r e r e t a i n e d in p o wer - do w n m o de . w h en exi t in g p o w e r - do wn, t h e se t t li n g tim e o f th e a m p l i f i e r w i ll e l a p s e b e f o r e th e o u t p u t s set t le t o t h eir co r r e c t val u es.
ad5383 rev. 0 | page 26 of 40 ad5383 interfaces the ad5383 contains both parallel and serial interfaces. furthermore, the serial interface can be programmed to be either spi, dsp, microwire, or i 2 c compatible. the ser/ par pin selects parallel and serial interface modes. in serial mode, the spi /i2c pin is used to select dsp, spi, microwire, or i 2 c interface mode. the devices use an internal fifo memory to allow high speed successive writes in parallel interface mode. the user can con- tinue writing new data to the device while write instructions are being executed. the busy signal indicates the current status of the device, going low while instructions in the fifo are being executed. in parallel mode, up to 128 successive instructions can be written to the fifo at maximum speed. when the fifo is full, any further writes to the device are ignored. to minimize both the power consumption of the device and the on-chip digital noise, the active interface only powers up fully when the device is being written to, i.e., on the falling edge of wr or the falling edge of sync . dsp, spi, microwire compatible serial interfaces the serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy-chain mode. daisy chaining allows many devices to be cascaded together to increase system channel count. the ser/ par pin must be tied high and the spi /i2c pin (pin 97) should be tied low to enable the dsp/spi/microwire compatible serial interface. in serial interface mode, the user does not need to drive the parallel input data pins. the serial interfaces control pins are sync , din, sclk standard 3-wire interface pins. dcen selects standalone mode or daisy-chain mode. sdo data out pin for daisy-chain mode. figure 3 and figure 5 show timing diagrams for a serial write to the ad5383 in standalone and daisy-chain modes. the 24-bit data-word format for the serial interface is shown in table 19 a /b . when toggle mode is enabled, this pin selects whether the data write is to the a or b register. with toggle disabled, this bit should be set to zero to select the a data register. r/ w is the read or write control bit. a4Ca0 are used to address the input channels. reg1 and reg0 select the register to which data is written, as shown in table 11. db11Cdb0 contain the input data-word. x is a dont care condition. standalone mode by connecting the dcen (daisy-chain enable) pin low, stand- alone mode is enabled. the serial interface works with both a continuous and a noncontinuous serial clock. the first falling edge of sync starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. any further edges on sync except for a falling edge are ignored until 24 bits are clocked in. once 24 bits have been shifted in, the sclk is ignored. in order for another serial transfer to take place, the counter must be reset by the falling edge of sync . table 19. 40-channel, 12-bit dac serial input register configuration msb lsb a /b r/ w 0 a4 a3 a2 a1 a0 reg1 reg0 db11 db10 db 9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x x
ad5383 rev. 0 | page 27 of 40 dai s y - c h ai n m o d e f o r sys t em s tha t co n t ain s e v e ra l de vices, t h e s d o p i n ma y be us e d to da isy - cha i n s e ver a l d e v i ces to get h er . t h is da i s y - cha i n m o de can be us ef u l in sys t em dia g n o s t ics an d in r e d u cing the n u m b e r o f se ri al i n t e rf a c e l i n e s. b y co nn ec tin g t h e d c en (d a i s y -c ha in ena b le) p i n hig h , da isy - cha i n m o de is e n a b le d . t h e f i rst fa l l in g e d ge o f sy n c st ar ts t h e wr i t e c y cle . th e sclk is con t i n uo us l y a p plie d to t h e i n p u t s h if t re g i ste r w h e n sy n c i s lo w . i f m o r e tha n 24 c l o c k p u ls es a r e a p p l ie d , the da t a r i p p les o u t o f th e shif t r e g i st e r a n d a p p e a r s on th e s d o lin e . this da t a is c l o c k e d o u t on t h e r i sin g edg e o f sclk and is va l i d o n t h e fa l l i n g e d ge. by co n n e c t i n g t h e s d o of th e f i r s t de v i ce t o th e d i n i n p u t o n th e n e xt d e vi ce i n t h e c h a i n , a m u l t i d e v ic e in t e r f ace is co n s t r uc t e d . t w e n ty -fo u r clo c k p u ls es a r e r e q u ir e d fo r e a ch de vice i n t h e syst em. ther efo r e , t h e t o t a l n u m b er o f clo c k c y cles m u s t e q ual 24n, w h er e n is t h e t o t a l n u m b er o f ad5 38x devices in th e c h ain. w h en t h e s e r i al tra n sf er t o al l devices is com p let e , sy n c is t a k e n h i gh . t h i s l a t c h e s th e i n p u t d a ta i n e a c h d e v i c e i n th e da isy - ch a i n an d p r e v en ts an y f u r t h e r d a t a f r o m b e i n g clo c k e d in t o t h e i n p u t shif t r e g i st er . i f th e s y n c is t a k e n hig h bef o r e 24 c l o c ks a r e clo c k e d in t o the p a r t , t h is is co n s ider e d a b a d f r am e and t h e d a t a is dis c a r de d . the s e r i al clo c k ma y b e ei t h er a co n t i n uo us o r a ga t e d clo c k. a co n t in uo us scl k s o ur ce can o n l y be us ed if i t c a n be a r ra n g e d th a t sy n c is h e l d lo w fo r t h e co r r e c t n u m b er o f clo c k c y cles. i n ga te d clo c k m o de, a b u rst clo c k co n t a i nin g t h e ex ac t n u m b er o f cl o c k c y cl es m u st b e u s e d and sy n c m u s t be ta k e n hig h a f t e r th e f i nal c l o c k to la t c h the da t a . re a d b a c k m o d e re a d b a ck m o d e is in v o k e d b y s e t t i n g t h e r/ w b i t = 1 i n th e se ri al i n p u t r e gis t e r w r i t e . w i th r / w = 1, bi ts a4 to a0, in as s o c i a t io n wi th b i ts reg1 and reg0, s e le c t t h e r e g i s t er t o be r e ad . th e r e ma i n in g da t a b i ts in t h e wr i t e s e q u e n ce a r e don t ca r e s. duri n g th e n e xt s p i w r i t e , th e da ta a p pea r i n g o n t h e s d o o u t p ut w i l l co n t a i n t h e d a t a f r om t h e p r e v io usly addr ess e d r e g i st er . f o r a r e ad o f a sin g le r e g i st er , t h e n o p co mman d can be us e d in c l o c k i n g o u t t h e da ta f r o m th e s e lec t ed r e g i s t er o n sd o . f i g u re 3 0 show s t h e re a d b a ck s e qu e n c e . f o r e x am p l e, to r e ad bac k t h e m r e g i s t er o f cha nne l 0 o n t h e ad5383, th e f o l l ow i n g s e qu e n c e s h ou l d b e i m pl e m e n te d. f i r s t , w r ite 0x404x x x t o th e ad5383 in p u t r e g i s t er . this co nf igur es th e ad5383 f o r r e ad m o de wi th t h e m r e g i s t er o f cha n n e l 0 s e lec t e d . n o te t h a t da ta b i ts d b 11 t o d b 0 a r e do n t ca r e s. f o l l o w this wi th a s e cond wr i t e , a n o p co n d i t ion, 0x000000. dur i n g t h is wr i t e , t h e da t a f r o m t h e m r e g i s t er is clo c k e d o u t on t h e d o u t l i n e , i . e . , d a t a c l o c k e d o u t w i l l c o n t a i n t h e d a t a f r o m t h e m r e g i s t er in b i ts d b 11 t o d b 0, a nd t h e t o p 10 b i ts con t a i n t h e addr ess info r m a t io n as p r e v io usly wr i t ten. i n r e ad b a ck m o d e , th e sy n c s i gn a l m u s t fr a m e th e d a t a . d a ta i s c l oc k e d o u t o n th e r i s i ng e d ge of s c l k a n d i s v a l i d on t h e f a l l i n g e d ge of t h e s c l k sig n al . i f t h e sc lk idles hig h b e tw e e n t h e wr i t e a nd r e ad op e r a t i o n s of a re a d b a c k op e r a t i o n , t h e f i r s t bit of d a t a i s c l o c k e d o u t on t h e fal l in g edge o f sy n c . 03731-0-019 24 48 sclk sync din sdo undefined selected register data clocked out nop condition input word specifies register to be read db23 db0 db0 db23 db23 db0 db0 db23 f i g u re 30. s e ri al r e adba ck o p er at i o n
ad5383 rev. 0 | page 28 of 40 i 2 c serial interface the ad5383 features an i 2 c compatible 2-wire interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the ad5383 and the master at rates up to 400 khz. figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. in selecting the i 2 c operating mode, first configure serial operating mode (ser/ par = 1) and then select i 2 c mode by configuring the spi /i2c pin to a logic 1. the device is connected to the i 2 c bus as a slave device (i.e., no clock is generated by the ad5383). the ad5383 has a 7-bit slave address 1010 1(ad1)(ad0). the 5 msb are hard- coded and the 2 lsb are determined by the state of the ad1 and ad0 pins. the facility to hardware configure ad1 and ad0 allows four of these devices to be configured on the bus. i 2 c data transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals that configure start and stop conditions. both sda and scl are pulled high by the external pull-up resistors when the i 2 c bus is not busy. start and stop conditions a master device initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high. a start condition from the master signals the beginning of a transmission to the ad5383. the stop condition frees the bus. if a repeated start condition (sr) is generated instead of a stop condition, the bus remains active. repeated start conditions a repeated start (sr) condition may indicate a change of data direction on the bus. sr may be used when the bus master is writing to several i 2 c devices and wants to maintain control of the bus. acknowledge bit (ack) the acknowledge bit (ack) is the ninth bit attached to any 8-bit data-word. ack is always generated by the receiving device. the ad5383 devices generate an ack when receiving an address or data by pulling sda low during the ninth clock period. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication. ad5383 slave addresses a bus master initiates communication with a slave device by issuing a start condition followed by the 7-bit slave address. when idle, the ad5383 waits for a start condition followed by its slave address. the lsb of the address word is the read/ wr ite ( r/ w ) bit. the ad5383 is a receive only device; when communicating with the ad5383, r/ w = 0. after receiving the proper address 10101 (ad1) (ad0) , the ad5383 issues an ack by pulling sda low for one clock cycle. the ad5383 has four different user programmable addresses determined by the ad1 and ad0 bits. write operation there are three specific modes in which data can be written to the ad5383 dac. 4-byte mode when writing to the ad5383 dacs, the user must begin with an address byte (r/ w = 0) after which the dac will acknowl- edge that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte; this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 31. a stop condition follows. this allows the user to update a single channel within the ad5383 at any time and requires four bytes of data to be transferred from the master. 3-byte mode in 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte each time. the device address byte is only required once; sub- sequent channel updates require the pointer byte and the data bytes. in 3-byte mode, the user begins with an address byte (r/ w = 0), after which the dac will acknowledge that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte. this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. this is then followed by the two data bytes. reg1 and reg0 determine the register to be updated. if a stop condition does not follow the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. this mode only requires three bytes to be sent to update any channel once the device has been initially addressed, and reduces the software overhead in updating the ad5383 channels. a stop condition at any time exits this mode. figure 32 shows a typical configuration.
ad5383 rev. 0 | page 29 of 40 1 0 1 0 1 ad1 ad0 r/w 0 0 0 a4 a3 a2 a1 a0 scl sd a scl sd a start cond by master ack by ad538x ack by ad538x address byte most significant byte least significant byte pointer byte msb ack by ad538x ack by ad538x stop cond by master reg1 reg0 msb lsb msb lsb 03731-0-020 f i g u re 31. 4-b y t e a d 53 8 3 , i 2 c w r ite o p er at ion 03731-0-021 scl s d a s d a scl s d a scl s d a scl start cond by master ack by ad538x msb address byte pointer byte for channel "n" most significant data byte pointer byte for channel "next channel" least significant data byte most significant data byte least significant data byte ack by ad538x ack by ad538x data for channel "n" data for channel "next channel" ack by ad538x 1 0 0 0 a 4 a 3a 2a 1 a 0 0 1 0 0 0 0 a 4a 3 a 2a 1 a 0 1 ad1 ad0 r / w r e g 1 r e g 0 msb l s b msb l s b msb ack by ad538x ack by ad538x ack by ad538x stop cond by master reg1 reg0 msb lsb msb lsb f i g u re 32. 3-b y t e a d 53 8 3 , i 2 c w r ite o p er at ion
ad5383 rev. 0 | page 30 of 40 2-b y t e m o de f o l l o w in g in i t ia liza t i o n o f 2-b y te m o de , t h e us e r ca n u p d a te c h a n n e l s seq u en tiall y . t h e device a d d r e s s b y t e i s o n l y r e q u i r ed o n ce an d t h e p o in t e r ad dr ess p o in t e r is co nf igure d fo r a u t o - i n cr em en t o r b u r s t m o d e . the us er m u st b e g i n w i t h an ad dr ess b y t e (r/ w = 0), a f t e r w h ich t h e d a c wi l l ack n o w le dge t h a t i t is p r ep ar e d t o r e cei v e da ta b y p u l l in g s d a lo w . th e addr es s b y t e is f o l l o w ed b y a sp e c if ic p o i n ter b y t e (0xff) t h a t ini t i a t e s t h e b u rst m o de o f o p er a t ion. t h e addr ess p o in ter ini t ia li zes to c h a nnel 0, t h e da t a fol l o w in g t h e p o in t e r is lo ade d t o cha n n e l 0, and t h e addr ess p o i n te r a u toma t i c a l l y i n c r e m e n t s to t h e ne x t a d dre s s . the reg0 and reg1 b i ts i n t h e da t a b y t e de t e r m in e w h ich r e g i st er w i l l b e u p d a te d . i n t h is m o d e , fol l o w in g t h e i n i t ia li za - ti o n , o n l y th e tw o d a ta b y t e s a r e r e q u i r ed t o u p da t e a c h a n n e l . the cha n ne l addr es s a u t o ma t i c a l l y in cr e m en ts f r o m a ddr es s 0 to c h an nel 3 1 a nd t h e n re t u r n s to t h e nor m a l 3 - b y te mo d e of o p era t ion. this m o d e a l lo ws t r a n smissio n o f da t a t o a l l cha n n e ls i n o n e b l o c k and r e d u ces t h e s o f t w a r e o v erh e ad i n co nf igur in g a l l cha n n e ls. a s t op co n d i t ion a t a n y t i m e ex i t s t h is m o de. t o g g l e m o d e is n o t su p p o r te d i n 2-b y te mo de. f i gur e 33 s h o w s a typ i cal co nf ig ura t io n. p a r a llel interf a c e the s e r / pa r p i n m u s t be tied lo w to ena b le the p a ral l e l in t e r f ace a nd di s a b l e t h e s e r i al i n t e r f aces. f i gur e 7 s h o w s t h e timin g dia g ram f o r a p a ralle l wr i t e . the p a ralle l in t e r f ace is c o n t r o ll ed b y th e f o ll o w i n g p i n s : cs pin a c ti v e l o w de vice s e lec t p i n. wr pin on the r i sin g e d g e o f wr , w i t h cs l o w , th e a d d r e s se s o n p i n s a4 t o a0 a r e la tch e d; da t a p r es e n t o n t h e da t a b u s is lo ade d in to t h e s e le c t e d i n pu t r e g i s t ers. reg0, reg1 pi ns the reg0 and reg1 p i n s dete r m in e t h e dest i n a t ion r e g i ster o f th e da ta bein g wr i t t e n t o the ad5383. s e e t a b l e 11. pins a4 to a 0 e a ch o f t h e 32 d a c cha n nels c a n b e ad dr ess e d indivi d u a l ly . pins db11 to d b 0 the ad5383 ac cep t s a s t ra ig h t 12-b i t p a ral l e l wo r d o n d b 11 t o d b 0, w h er e d b 11 is t h e ms b and d b 0 is t h e l s b . 1 0 1 0 1 ad1 ad0 r/w a7 = 1 a6 = 1 a5 = 1 a4 = 1 a3 = 1 a2 = 1 a1 = 1 a0 = 1 start cond by master address byte pointer byte most significant data byte channel 0 data least significant data byte ack by converter msb ack by converter ack by ad538x ack by ad538x most significant data byte channel 1 data least significant data byte ack by converter ack by converter most significant data byte channel n data followed by stop least significant data byte ack by converter ack by converter stop cond by master reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb scl sda scl sda scl sda scl sda 03731-0-022 f i g u re 33. 2-b y t e , i 2 c w r ite o p er ati o n
ad5383 rev. 0 | page 31 of 40 micr oprocessor interf a c ing p a r a llel int e r f a c e the ad5383 can b e in t e r f aced t o a va r i ety o f 16-b i t micr o c on- tr ol lers o r ds p p r o c es s o rs. f i gur e 35 s h o w s t h e ad5383 fa mil y i n te r f a c e d to a g e ne r i c 1 6 - b i t mi c r o c on t r ol l e r / d s p pro c e s s o r . the lo w e r addr es s lin e s f r o m t h e p r o c e s s o r a r e co nn e c t e d t o a0Ca4 on the ad5383. th e u p p e r addr es s lines a r e deco de d to prov i d e a cs , ld a c s ig nal fo r t h e a d 53 83. th e f a s t i n te r f ace timin g o f t h e ad5383 al lo ws dir e c t in t e r f ace t o a wide va r i ety o f micr o c o n t r ol lers a nd dsp s , as sh o w n i n f i gur e 35. a d 53 83 to mc 68 hc 11 t h e se ri al pe ri p h e r al in t e rf a c e (s p i ) o n th e m c 6 8 h c 1 1 i s co nf igur e d fo r m a ster m o de ( m s t r = 1), c l o c k p o la r i ty b i t (cpo l) = 0, a nd t h e c l o c k p has e b i t (cph a) = 1. th e s p i is co nf igur e d b y w r i t in g t o t h e s p i co n t r o l r e g i st er (s pcr)s e e th e 68 h c 11 u s er m a n u al . sck o f th e 68h c11 dr i v es th e s c l k o f th e ad5383, th e m o s i o u t p u t dr i v es the s e r i al da ta line (d in ) o f th e ad5383, a nd t h e miso in p u t is dr i v en f r o m d ou t . t h e s y nc sig n al is der i v e d f r o m a p o r t lin e (pc7). w h en da ta is bein g tra n smi t ted t o t h e ad53 83, th e s y n c lin e is t a k e n lo w ( p c 7 ) . d a t a a p p e ar i n g on t h e m o si output i s v a l i d on t h e fal l in g edg e o f s c k. s e r i al da t a f r o m th e 68 h c 1 1 is tra n smi t t e d in 8- b i t b y t e s wi t h o n ly eig h t fa l l in g clo c k e d ges o c c u r r in g in th e tra n sm i t c y cle . 03734-0-004 mc68hc11 ad5383 miso mosi sck pc7 sdo reset ser/par din sclk sync spi/i2c dv dd f i gur e 3 4 . ad53 83 -t o - mc68 h c 11 inter f a c e 03734-0-005 controller/ dsp processor* ad5383 address decode upper bits of address bus data bus d15 d0 a4 a3 a2 a1 a0 r/w a4 a3 a2 a1 a0 wr reg1 reg0 d11 d0 cs ldac *additional pins omitted for clarity f i gure 35. a d 5 3 8 3 - t o - p a r a ll el i n te r f ace
ad5383 rev. 0 | page 32 of 40 a d 53 83 to p i c 1 6 c 6x/ 7 x the p i c16c6x/7x syn c hr on o u s s e r i al p o r t (ss p ) is co nf igur ed as a n s p i mas t er wi t h the c l o c k p o la r i ty b i t = 0. this is don e b y w r i t in g t o th e syn c h r o n o u s se rial po r t c o n t r o l r e gi s t e r (ss p co n). s e e th e pi c16/17 micr o c o n tr ol ler u s er m a n u al . i n this exa m p l e i/o , p o r t ra1 is b e in g us ed t o p u ls e sy n c an d ena b le t h e s e r i al p o r t o f th e ad5383. this micr o c o n tr ol ler tra n sf e r s o n l y e i gh t b i t s o f d a ta d u ri n g ea c h se rial tra n sf e r op e r a t i o n ; t h e r e f ore, t h re e c o ns e c ut ive re a d / w r i te op e r at i o ns ma y b e n e e d e d dep e n d in g on t h e m o de. f i gur e 36 sh o w s t h e co nne c t io n di a g r a m. 03734-0-006 pic16c6x/7x ad5383 sdi/rc4 sdo/rc5 sck/rc3 ra1 sdo reset ser/par din sclk sync spi/i2c dv dd f i g u re 36. a d 5 3 8 3 - t o - pic 1 6c6x / 7 x in t e r f ace a d 53 83 to 8 0 5 1 the ad5383 r e q u ir es a c l o c k s y n c hr o n ized t o th e s e r i al da t a . the 8051 s e r i al in t e r f ace m u s t t h er ef o r e be op era t e d in m o de 0 . i n t h is m o d e , s e r i a l d a t a en ters a nd ex i t s t h r o u g h rx d , a nd a s h if t c l o c k is ou t p u t on txd . f i gur e 37 s h o w s ho w th e 8051 is co nnec t e d t o t h e ad5383. b e ca us e th e ad5383 s h if ts da ta o u t o n th e ri si n g edg e o f th e s h i f t c l oc k a n d la t c h e s da ta i n o n th e fal l in g edge , th e s h if t c l o c k m u st be in v e r t ed . th e ad5383 r e q u ir es i t s da ta t o be ms b f i rs t. s i n c e the 8051 o u t p u t s the ls b f i r s t , th e tra n smi t r o u t in e m u s t tak e th i s in t o a c co un t . 03734-0-007 8xc51 ad5383 rxd txd p1.1 sdo reset ser/par din sclk sync spi/i2c dv dd f i gur e 3 7 . ad53 83 -t o - 805 1 int e r f a c e a d 53 83 to a d s p -21 01/ a d s p -21 0 3 f i gur e 38 s h o w s a s e r i al in t e r f ac e betw een t h e ad5383 a nd t h e ads p -2101/ads p -2103. th e ads p -2101 /ads p - 2103 sh o u ld b e s e t up to op e r a t e i n sp o r t t r ans m it a l te r n a t e f r am i n g mo d e . the ads p -2101 /ads p - 2103 s p o r t is p r og ra mmed thr o ug h t h e sp or t c o n t rol re g i ste r and shou l d b e c o nf i g u r e d as fol l ows: in t e r n a l clo c k op era t ion, ac t i v e lo w f r a m in g, a nd 16- b i t w o r d len g t h . t r a n smi s sio n is in i t ia t e d b y wr i t in g a w o r d t o t h e tx r e g i s t er a f t e r t h e s p o r t has b e en ena b le d . 03734-0-008 adsp-2101/ adsp-2103 ad5383 dr dt sck tfs rfs sdo reset ser/par din sclk dv dd spi/i2c sync f i gur e 3 8 . ad53 83 -t o - adsp -210 1/ adsp -2 10 3 int e r f a c e
ad5383 rev. 0 | page 33 of 40 appli c a t ion inf o rma t ion po wer suppl y dec o upling i n an y cir c ui t w h er e acc u rac y is im p o r t an t, ca r e f u l co n s idera- t i on of t h e p o we r supply an d g r ou nd re tu r n l a y o ut h e lp s to en s u r e t h e ra te d p e r f o r ma n c e . th e p r i n t e d cir c ui t b o a r d o n whic h t h e ad5 383 is m o un t e d s h o u ld b e desig n e d s o tha t the a n a l o g a nd dig i t a l s e c t io n s a r e s e p a r a te d an d conf in e d to cer t a i n a r eas o f th e bo a r d . i f the ad5383 is in a sys t em w h er e m u l t i p le de vice s r e q u ir e a n a g nd- t o - d g nd co nne c t io n, t h e co nne c t io n shou ld b e m a de a t o n e p o in t o n ly , a st a r g r o u nd p o in t est a b l ish e d as clos e t o t h e de vice as p o ssib le . f o r s u p p lies wi t h m u l t i p le p i n s (a v dd , d v dd ), th es e p i n s sh o u l d be tied t o g e t h er . the ad5383 sho u ld ha v e am p l e s u p p l y b y p a s- sin g o f 10 f in p a ral l e l wi t h 0.1 f o n eac h s u p p l y , lo ca t e d as cl o s e to t h e p a c k age a s p o ss i b l e an d i d e a l l y r i g h t up ag ai n s t t h e de vice . the 10 f ca p a ci t o rs a r e t h e t a n t al um b e ad ty p e . th e 0.1 f ca p a ci t o r s h o u ld ha v e lo w ef f e c t i v e s e r i es r e sis t a n c e (es r ) a nd ef f e c t i v e ser i es in d u c t a n ce (es i ), lik e th e co mmo n cera mic ty p e s t h a t p r o v id e a lo w im p e dan c e p a t h t o g r o u n d a t h i g h f r e q u e nc i e s , to h a nd l e t r a n s i e n t c u r r e n t s du e to i n te r n a l log i c swi t ching. the p o w e r s u p p l y lin e s o f th e ad5383 sh o u ld us e as la rg e a t r ace as p o s s ib le t o p r o v ide lo w im p e dance p a t h s a nd r e d u c e t h e ef fe c t s o f g l i t ches o n t h e p o w e r s u p p l y line . f a st sw i t chin g sig n als s u c h as clo c ks sh o u ld be s h ie lde d wi t h dig i tal g r o u nd t o a v oi d r a d i a t i n g noi s e to ot he r p a r t s of t h e b o ar d, an d s h ou l d ne ver b e r u n n e a r t h e r e fer e n c e in p u ts. a g r o u nd li n e r o u t e d bet w een t h e d in a nd scl k li n e s wi l l h e l p r e d u c e cr o sst a l k betw een t h em ( t his is n o t r e q u ir ed o n a m u l t i l a y er bo a r d b e ca us e t h er e w i l l b e a s e p a ra t e g r o u n d pl an e , b u t s e p a ra t i n g t h e lin e s wi l l he l p ). i t is ess e n t ia l t o mini mi ze n o is e o n t h e v in and refin lin e s. a v oi d c r o s s o ve r of d i g i t a l a n d a n a l o g s i g n a l s . t r a c e s on opp o s i t e sides o f t h e b o a r d sh o u l d r u n a t r i g h t a n g l es to e a ch o t h e r . this r e d u ce s th e e f f e ct s o f f eed th r o ugh th r o ugh t h e boa r d . a m i cr o- st r i p te chni qu e is b y f a r t h e b e st , b u t is not a l w a y s p o ss ibl e wi t h a do ub l e -side d b o a r d . i n t h is te chniq u e, t h e com p on e n t side of t h e b o a r d is de dica t e d t o t h e g r oun d plan e w h i l e sig n al t r aces a r e place d o n t h e s o lder side . t y p i c a l c o nfigur a t i o n circu i t f i gur e 39 s h o w s a typ i cal co nf ig ura t io n f o r th e ad5383-5 w h en c o n f i g u r e d f o r u s e w i t h a n e x te r n a l re f e re nc e. i n t h e c i rc u i t s h own, al l a g nd , s i gn al_g nd , an d d a c_ gnd p i n s a r e tie d to get h er to a comm on a g nd . a g nd and d g nd a r e co nnec t e d t o g e t h er a t the ad53 83 de vice . o n p o w e r - u p , th e ad5383 def a u l ts t o ext e r n al r e f e r e n c e op era t ion. al l a v dd lin e s a r e co nn e c t e d tog e t h er an d dr i v en f r o m t h e s a m e 5 v s o ur ce . i t is r e co mmen d e d t o deco u p le c l os e t o th e de vic e wi th a 0.1 f cera mic an d a 1 0 f t a n t a l u m c a p a ci t o r . i n t h is a p plic a t ion, t h e r e f e r e n c e f o r the ad5383 -5 is p r o v ided ext e r n a l l y f r o m ei th er a n adr421 o r ad r431 2.5 v r e f e r e n c e . s u i t ab l e ext e r n al r e f e r e n c es f o r th e ad5383 -3 inc l ude the ad r2 80 1.2 v re f e re nc e. t h e r e f e re nc e s h ou l d b e d e c o up l e d at t h e refo ut/refi n p i n o f th e de vice wi th a 0.1 f ca p a ci t o r . 03734-0-009 adr431/ adr421 ad5383-5 avdd dvdd signal gnd dac gnd dgnd vout31 vout0 agnd refout/refin refgnd 0.1 f 10 f 0.1 f 0.1 f avdd dvdd f i gure 39. t y pic a l configur ation with e x tern al refe r e nce f i gur e 40 sh o w s a ty p i ca l co nf ig ura t io n w h en u s in g t h e in t e r n a l r e f e r e n c e . on p o w e r - u p , th e ad5383 defa u l ts t o a n ext e r n al r e fer e n c e; t h er efo r e , t h e in t e r n al r e fer e n c e n e e d s t o b e co nf igur ed an d t u r n e d o n via a wr i t e t o the ad5383 co n t r o l r e g i s t er . c o n t r o l reg i st er bi t c r 10 al lo ws t h e us er ch o o s e t h e re f e re nc e v a lu e ; bit c r 8 i s u s e d to s e l e c t t h e i n t e r n a l re f e re nc e. i t i s re c o m m e n d e d to u s e t h e 2 . 5 v re f e re nc e w h e n a v dd = 5 v , a nd t h e 1.25 v refer e n c e w h en a v dd = 3 v . 03734-0-010 ad5383 avdd dvdd signal gnd dac gnd dgnd vout31 vout0 agnd refout/refin refgnd 0 .1 f 10 f 0.1 f 0.1 f avdd dvdd f i gure 40. t y pic a l configur ation with i n tern al refe r e nce dig i tal conn ec tio n s ha v e be en omi t t e d f o r c l a r i t y . th e ad5383 co n t a i n s an in t e r n al p o w e r - o n r e s e t cir c ui t wi t h a 10 m s b r o w n o u t time . i f th e p o w e r s u p p l y ra m p ra t e ex ceed s 10 m s , th e use r sh o u ld r e se t th e a d 5383 a s pa r t o f th e in i t i a liz a ti o n p r o c es s t o en s u re t h e calib r a t io n da t a g e ts lo ade d co r r e c t l y in t o th e de v i ce .
ad5383 rev. 0 | page 34 of 40 ad5383 monit o r func tion the ad5383 con t a i n s a c h ann e l m o ni t o r f u n c tio n tha t co n s is ts o f a m u l t i p lexer addr ess e d vi a t h e i n t e r f ac e, a l lo win g an y chan - ne l output to b e route d to t h i s pi n for mon i tor i ng u s i n g an ex ter n a l ad c. the cha n nel mo ni to r f u n c t i o n m u st b e enab le d i n t h e c o n t ro l re g i ste r b e f o re a n y ch an n e l s are route d to m o n_o u t . t a b l e 18 co n t a i n s th e deco din g inf o r m a t io n n e ed ed t o r o u t e a n y c h a n n e l t o m o n _ o u t . se l e ct i n g c h a n n e l a ddr es s 63 thr e e-s t a t es m o n_ o u t . f i gur e 41 s h o w s a typ i cal m o ni t o r i n g cir c ui t im p l em en t e d usin g a 12-b i t sar ad c in a 6-lead sot - 23 p a c k a g e . the con t r o l l er o u t p u t p o r t s e lec t s t h e cha n n e l t o b e mo ni t o r e d , an d t h e in p u t p o r t r e ads t h e con v er t e d da ta f r o m t h e ad c. t o ggle mode fu nc tion t h e t o ggl e m o de fu n c ti o n all o w s a n o u t p u t s i gnal t o be g e n e ra - te d u s i n g t h e ld a c co n t r o l sig n al tha t s w i t ch es between tw o d a c da t a r e g i sters. this f u n c t i on is co nf igur e d usin g t h e s f r co n t r o l r e g i s t er as f o l l o w s. a wr i t e wi th reg1 = reg0 = 0 a nd a4Ca0 = 01100 s p ecif ies a con t r o l r e g i s t er wr i t e . the t o g g l e m o de f u n c tio n is ena b led in g r ou ps o f eig h t c h anne ls usin g b i ts cr3 t o cr0 in t h e con t r o l r e g i st er . s e e the ad5 383 co n t r o l r e gi s t e r d e sc ri p t i o n . f i g u r e 4 2 s h o w s a b l oc k dia g ra m o f t o ggl e m o de im p l em en ta ti o n . e a ch o f th e 32 d a c c h a n n e ls o n t h e ad5383 co n t a i n a n a and b da ta r e g i s t er . n o t e tha t t h e b r e g i s t ers can o n l y b e lo ade d w h en t o g g l e m o de is ena b le d . th e seq u en ce o f ev en t s w h e n co n f i g uri n g th e a d 5383 f o r t o ggl e mo d e i s 1. ena b le t o g g l e mo de fo r t h e r e q u ir e d cha n ne ls v i a t h e c o n t ro l re g i ste r . 2. loa d d a ta t o a r e gi s t e r s . 3. loa d d a ta t o b r e gi s t e r s . 4. ap p l y ld a c . the ld a c i s used t o s w i t c h bet w een t h e a a n d b r e gis t e r s i n deter m ini n g t h e a n a l o g o u t p ut. the f i rst ld a c co nf igur es th e o u t p u t t o r e f l ec t da ta in t h e a r e g i s t ers. this m o de o f f e rs sig n if- ica n t ad va n t a g es if th e us er wan t s t o g e n e r a t e a s q u a r e wa ve a t t h e o u t p ut o f a l l 32 cha nnels, as mig h t b e r e q u ire d to dr i v e a liq u id cr ys tal bas e d va r i a b le o p t i cal a t ten u a t o r . i n this cas e , t h e us er wr i t es t o t h e co n t r o l r e g i s t e r a n d ena b les t h e t o g g l e f u n c - tio n b y s e t t in g cr3 t o cr2 = 1 , th us ena b lin g t h e f o ur g r o u ps o f eig h t fo r t o g g l e m o de o p er a t io n. th e us er m u s t t h e n lo ad da t a t o al l 32 a an d b r e g i s t ers. t o g g lin g ld a c se t s th e o u t p u t val u es t o r e f l e c t t h e da t a in t h e a an d b r e g i st ers. th e ld a c s f r e q uen c y det e r m i n es t h e f r e q uen c y o f t h e s q u a r e wa v e ou t p u t . t o g g l e m o de is dis a b l e d v i a t h e co n t r o l r e g i s t er . the f i rs t ld a c fol l o w in g t h e di s a b l in g o f t h e t o g g l e m o de u p da t e s t h e ou t p u t s wi t h t h e da t a con t a i ne d i n t h e a r e g i sters. thermal m o nit o r fu nc tio n the ad5383 con t a i n s a t e m p er a t ur e sh u t do wn f u n c tion t o prote c t t h e ch ip i n c a s e m u lt ipl e output s are s h or te d. t h e s h or t cir c ui t c u r r en t o f e a ch o u t p u t am plif ier is ty p i c a l l y 40 ma. o p era t ing the ad5383 a t 5 v le ads t o a p o w e r dis s i p a t io n o f 200 mw p e r sho r t e d a m p l if ier . w i t h f i v e c h anne ls s h o r t e d , this leads t o a n extra wa t t o f p o w e r dis s i p a t io n. f o r th e 100-lead lqf p , t h e ja is typ i cal l y 44c/w . the t h er mal mo ni t o r is enab le d b y t h e us er vi a cr6 i n t h e co n t r o l r e g i s t er . the o u t p u t am plif iers o n th e ad5383 a r e a u t o ma t i cal l y p o w e r e d do wn if t h e die t e m p er a t ur e exce e d s a p p r o x ima t e l y 130c. af t e r a t h er mal s h u t down has o c c u r r ed , t h e us er can r e - e na b l e t h e p a r t b y exe c u t in g a s o f t p o w e r - u p if th e tem p era t ur e has dr o p p e d belo w 130c o r b y t u r n in g o f f th e t h er mal m o ni t o r f u n c t i o n v i a t h e con t r o l r e g i st er . ad7476 gnd sdata cs sclk avcc v in mon_out agnd din sync sclk dac_gnd signal_gnd vout0 vout31 avcc ad5383 output port input port controller 03734-0-011 a d 7 8 0 / a d r 4 3 1 refout/refin mon_in1 mon_in2 avcc f i gure 41. t y pic a l c h ann e l m o n i to ri ng circuit
ad5383 rev. 0 | page 35 of 40 12-bit dac dac register input data input register data register b data register a a/b v out ldac control input 03732-0-015 f i g u re 42. t o gg l e m o de f u nc t i on attenuator attenuator attenuator attenuator awg awg fibre fibre dwdm out optical switch 11 12 1n? 1 1n dwdm in ad5383, 32-channel, 12-bit dac n:1 multiplexer 16-bit adc controller tia/log amp (ad8304/ad8305) adg731 (32:1 mux) ad7671 (0-5v, 1msps) photodiodes add ports drop ports 03734-0-013 f i g u re 43. oa dm u s ing t h e a d 53 8 3 as p a r t of an o p t i c a l at tenuat or o p t i c a l at t e n u at o r s b a s e d o n i t s hig h cha n nel co un t , hig h r e s o l u t i on, m o n o to nic be ha vio r , a nd hig h leve l o f in teg r a t io n, t h e ad5 383 is ideal l y t a rget e d a t o p t i c a l a t t e n u a t io n a p plica t io n s us e d in d y namic ga in e q ualizers, va r i a b le o p tical a t t e n u a t o r s (v o a ), a nd o p tic a l add- dr o p m u l t i p lexers (o ad m). i n t h es e a p pli c a t ion s , e a ch wa vele n gt h is i ndivid u a l ly ex t r ac te d usin g an a r r a ye d w a ve guide; i t s p o w e r is m o n i t o r e d usin g a ph o t o d io d e , t r a n sim p e d - anc e am pl i f i e r an d a d c i n a cl o s e d - l o o p c o n t rol s y ste m . t h e ad5383 co n t r o l s th e o p t i cal a t t e n u a t o r f o r eac h wa v e l en gth, en s u r i n g t h a t t h e p o w e r is e q ual i ze d i n al l w a v e l en gt h s b e fo r e b e i n g m u l t i p lexe d o n t o t h e f i b e r . this p r e v en ts info r m a t io n loss a nd s a t u ra t i o n f r o m o c c u r r in g a t am plif ic a t ion st a g es f u r t h e r alo n g th e f i b e r .
ad5383 rev. 0 | page 36 of 40 utilizing the ad5383 fifo the ad5383 fifo m o de o p timizes t o tal sys t em u p da t e r a t e s in a p pl i c a t i o ns w h e r e a l a r g e n u mb e r of ch an nel s ne e d to b e u p da ted . fifo m o de is o n l y a v a i la b l e w h en p a ral l e l in t e r f ace m o de is se lec t e d . th e fifo_e n p i n is used t o en a b le t h e fifo . t h e s t a t us o f fifo_en is sam p led d u r i n g t h e in i t ializa tio n s e q u en ce . th er ef o r e , th e fifo s t a t us can o n l y b e c h a n g e d b y r e s e t t in g t h e de vice . i n a t e les c op e t h a t p r o v ides fo r t h e can c e l - la t i on o f a t m o sph e r i c dis t o r t i on, fo r exa m ple , a la rg e n u m b er o f c h a n n e ls n e e d to be u p da t e d in a sh o r t p e r i o d of tim e . i n s u c h sys t em s, as ma n y as 320 c h a n n e ls n e e d t o b e u p da t e d wi thin 25 s t o 30 s. thr e e-h u ndr ed-tw e n t y c h a n n e ls r e q u ir e th e us e o f 10 ad5383s. w i t h fifo m o de ena b le d , the da ta wr i t e c y c l e time is 40 n s ; t h er ef o r e eac h g r o u p co n s is tin g o f 32 c h a nne ls can be f u l l y lo aded in 1.28 s. i n fif o m o de , a com p let e g r o u p o f 32 c h a n n e ls u p da t e s in 11.5 s. the tim e t a k e n t o u p da te al l 32 0 c h a n n e ls is 11.5 s + 9 1.28 s = 23 s. f i gur e 44 s h o w s t h e fifo o p era t io n sc h e m e . group a chnls 0-31 group b chnls 32-63 group c chnls 64-95 group d chnls 96-127 group e chnls 128-159 group f chnls 160-191 group g chnls 192-223 group h chnls 224-255 group i chnls 256-287 group j chnls 288-319 time to update 320 channels = 23 s 1.28 s 11.5 s 11.5 s 1.28 s fifo data load group a fifo data load group b output update time for group a 1.28 s 11.5 s fifo data load group j output update time for group j output update time for group b 03734-0-014 f i gure 44. using fifo mode 320 chann e ls up dat e d in u n d e r 25 s
ad5383 rev. 0 | page 37 of 40 outline dimensions top view (pins down) 1 25 26 51 50 75 76 100 14.00 bsc sq 0.50 bsc 0.27 0.22 0.17 1.60 max seating plane 12 typ 0.75 0.60 0.45 view a 16.00 bsc sq 12.00 ref 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bed f i g u re 45. 1 00-l e a d l e aded q u ad f l a t pack [l qfp ] (st - 10 0) di me nsio ns sho w n i n mi ll im e t e r s ordering guide m o d e l r e s o l u t i o n t e mper a t ur e ra n g e av dd ra n g e ou t p u t channels linearit y err o r p a ck age description p a ck age op t i o n ad5383bst -3 12 bits C40c to +85c 2.7 v to 3.6 v 32 1 lsb 100-l e ad l q fp st -100 ad5383bst -3-r eel 12 bits C40c t o +85c 2.7 v t o 3.6 v 32 1 lsb 100-l e ad l q fp st -100 ad5383bst -5 12 bits C40c to +85c 4.5 v to 5.5 v 32 1 lsb 100-l e ad l q fp st -100 ad5383bst -5-r eel 12 bits C40c t o +85c 4.5 v t o 5.5 v 32 1 lsb 100-l e ad l q fp st -100 e v al - a d 5 3 8 3 e b e v alua t i o n k i t
ad5383 rev. 0 | page 38 of 40 notes
ad5383 rev. 0 | page 39 of 40 notes
ad5383 rev. 0 | page 40 of 40 notes p u r c h a se o f li c e n s e d i 2 c c o m p on en t s o f an a l og devi c e s or on e of i t s subli c en s e d a s s oci a t e d c o m p a n i e s c o n v ey s a li c e n s e f o r t h e pur c h a ser un der t h e p h i li p s i 2 c p a te nt r i ghts t o us e the s e co mpo n e n ts in an i 2 c sy st em , pr o v i d e d t h a t t h e sy st em c o n f orm s t o t h e i 2 c stand a rd sp ecif ica t ion as d e f i ned b y p h il ips. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d03734C0C 5/04(0)

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